Commit Graph

183 Commits

Author SHA1 Message Date
82baacfd5b Fixed race condition giving garbage data on debug register write prints and ordering of reg write and instr fetch debug prints 2023-03-12 08:55:40 +00:00
9230900b75 fixed verilator lint warnings relating code enabled with debug options from config.v 2023-03-12 08:12:01 +00:00
aabe62b4c9 Added missing copyright and license notice 2023-03-09 06:13:34 +00:00
11624ca2d2 Added the OUT instruction to be able to properly address I/O and moved printing logic to a device on the I/O space. Also added IRET which is basically just a RET in this case 2023-03-09 06:03:13 +00:00
9de83fd7c1 Added partial support for the software interrupt INT instruction 2023-03-08 07:26:28 +00:00
d93c92c005 Slight adjustment to README 2023-03-06 21:57:36 +00:00
8070d4e58a Improved build system's handling of verilator 2023-03-05 23:11:18 +00:00
e8b84a38b6 Updated README.md about verilator 2023-03-05 06:37:07 +00:00
99cbc49e95 Wrote a more complete testbench for verilator, switched from lx2 to fst and fixed cpu clock frequency calculation 2023-03-05 00:10:55 +00:00
5705b8e8a5 Added support for Verilator! 2023-03-04 08:37:43 +00:00
ba52ff89e6 Fixed most problems verilator's linter found 2023-03-04 06:22:28 +00:00
59ec1b7a15 Removed remnants of the old memory addressing system 2023-03-03 20:43:25 +00:00
b00cd988cf Cleaned up boot_code 2023-03-03 19:36:28 +00:00
e1bb98c0f0 Updated toolchain versions and run project through aspell 2023-03-03 06:54:33 +00:00
f60084344e Overhauled cpu frontend. Made memory byte addressable (necessary), cleaned up state machine and fixed small bug with MOV 2023-03-03 06:29:06 +00:00
70a9ce6368 Forgot to remove it from proc_state_def.v 2023-02-26 02:48:39 +00:00
f7d76f1944 Removed useless state in the state machine and ran the project through aspell 2023-02-26 02:46:43 +00:00
0c36e9d78c Added message about compilation process on the compiler and fixed Makefile dependencies 2023-02-25 01:42:45 +00:00
6e8d951360 Increased the accessible memory and got the Mandelbrot renderer working under the brainfuck compiler! 2023-02-24 17:38:23 +00:00
6ea34a3525 Added MOV Immidiate to REG/MEM 2023-02-24 15:25:45 +00:00
5af6d720c3 Fixed ADD again and some memory read logic. Compiler runs the default brainfuck message program!! 2023-02-24 14:10:07 +00:00
3e484a0ceb Added register indirect unconditional jump 2023-02-24 13:04:32 +00:00
9ed3dc3312 Fixed bug introduced in a previous commit about fixing ADD 2023-02-24 12:48:03 +00:00
96b7a4d298 Added the SUB instruction (piggybacking off of ADD) AND THE COMPILER FINISHES GENERATING CODE!! 2023-02-24 12:47:32 +00:00
808827cbdd Fixed arg bug in ADD 2023-02-24 11:54:13 +00:00
355c673a37 Added a POP instruction 2023-02-24 11:31:15 +00:00
c3580848de Added bitwise TEST instruction 2023-02-24 10:08:01 +00:00
abee49d6c3 Implemented PUSH instruction, fixed register addressing bug and a RET bug 2023-02-24 07:32:27 +00:00
a189da249c Added STOS instruction. Native brainfuck compiler started generating code! 2023-02-24 05:01:55 +00:00
e684db8348 Added support to CMP for compare memory to opcode parameter, added support for both PROC_DE_LOAD_?_PARAM and PROC_MEMIO_READ at the same command and associated changes 2023-02-24 02:18:48 +00:00
c4ac55d4c3 Implemented the RET instruction,fixed CALL bug, clarified MOD naming and usage 2023-02-23 14:48:48 +00:00
1efef45266 Added missing license notices 2023-02-22 01:58:08 +00:00
cac01f0333 Fixed Makefile bug 2023-02-22 01:51:14 +00:00
7fde422341 Added Microcode support, Stack, implemented the CALL instruction in microcode and grouped the wires on the decoder module 2023-02-22 01:28:23 +00:00
619702384b Wrote an optimised native brainfuck compiler intended to be the default program running on release v0.1 utilising a good precentage of the 8086 instruction set 2023-02-19 21:42:59 +00:00
e2e9a92832 Cleaned the decoder a bit and laid down some of the groundwork for microcode 2023-02-19 16:22:23 +00:00
e6c9c722e3 Run the project through aspell and tweaked the README 2023-02-19 00:52:52 +00:00
fd4a9b5442 Fixed register addressing bug, mem read endianness, cleaned up code and added a provisional project logo 2023-02-19 00:20:53 +00:00
82bd859874 Moved the decoding of opcodes into a separate module and optimised memory reads 2023-02-17 18:08:09 +00:00
ed3d7101d3 Further improved build system and changed brainfuck print message 2023-02-16 23:26:32 +00:00
ded47555a5 Improved build system and project directory structure 2023-02-16 01:52:02 +00:00
5e0c990394 It is Turing complete! Running the Mandelbrot renderer with the brainfuck interpreter. Improved addressing modes and added CMP immediate with register instruction 2023-02-15 03:54:12 +00:00
f4d28cf4c8 Added 16bit unaligned register indirect writes, fixed some MOV bugs, clean up code names and data flow 2023-02-15 01:28:02 +00:00
c3563457c5 Finished MOV Reg/Mem to/from register 2023-02-14 15:49:29 +00:00
f97f4625e6 Added unconditional jumps and support for signed addition 2023-02-14 14:48:35 +00:00
037f6dd7da Added support for writing to memory 2023-02-14 13:13:40 +00:00
7c1067088c Properly licensed the project and run it through aspell 2023-02-13 16:49:17 +00:00
0d4221f9de Added config file (mainly for debug verbosity) and kind of patched some weird behaviour when clock is stopped 2023-02-13 15:24:21 +00:00
16e02e0788 Added conditional jump support! 2023-02-13 10:36:37 +00:00
923bf07c72 Fixed ALU bug and added missed updates to the Wbit 2023-02-12 01:28:37 +00:00