Efthimis/9086
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A CPU that aims to be binary compatible with the 8086 ISA, focused on optimisation and flexibility.
75 Commits 2 Branches 4 Tags 1.8 MiB
Verilog 66.9%
Makefile 9.9%
Assembly 9.4%
Shell 6.9%
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(Tim) Efthimis Kritikos 99cbc49e95 Wrote a more complete testbench for verilator, switched from lx2 to fst and fixed cpu clock frequency calculation
2023-03-05 00:10:55 +00:00
boot_code Wrote a more complete testbench for verilator, switched from lx2 to fst and fixed cpu clock frequency calculation 2023-03-05 00:10:55 +00:00
readme_files Fixed register addressing bug, mem read endianness, cleaned up code and added a provisional project logo 2023-02-19 00:20:53 +00:00
system Wrote a more complete testbench for verilator, switched from lx2 to fst and fixed cpu clock frequency calculation 2023-03-05 00:10:55 +00:00
.gitignore Wrote a more complete testbench for verilator, switched from lx2 to fst and fixed cpu clock frequency calculation 2023-03-05 00:10:55 +00:00
8086_documentation.md Overhauled cpu frontend. Made memory byte addressable (necessary), cleaned up state machine and fixed small bug with MOV 2023-03-03 06:29:06 +00:00
common.mk Wrote a more complete testbench for verilator, switched from lx2 to fst and fixed cpu clock frequency calculation 2023-03-05 00:10:55 +00:00
COPYING Properly licensed the project and run it through aspell 2023-02-13 16:49:17 +00:00
gtkwave_savefile.gtkw Wrote a more complete testbench for verilator, switched from lx2 to fst and fixed cpu clock frequency calculation 2023-03-05 00:10:55 +00:00
Makefile Added support for Verilator! 2023-03-04 08:37:43 +00:00
README.md Updated toolchain versions and run project through aspell 2023-03-03 06:54:33 +00:00

README.md

9086 logo

A CPU that aims to be binary compatible with the 8086 and with as many optimisations as possible

Progress

  • Executing code
  • Is Turing complete
  • Can boot up MS-DOS / FreeDOS
  • Is completely binary compatible
  • Is pipelined
  • Is Out of Order
  • Is superscalar
  • Has been successfully synthesized

Simulating it

To simulate this project you need Icarus Verilog, bin86, GNU make, xxd and the posix coreutils. After that you can run make on the top level directory and it should build everything and start the simulation

At the time of development the versions used are :

  • Icarus Verilog version 11.0 (stable)
  • bin86 version: 0.16.21
  • GNU Make 4.4.1
  • xxd 2022-01-14
  • GNU coreutils 9.1

License

All parts of this project are licensed under the GNU General Public License version 3 or later