c527a053a6Peripherals/ascii_to_HD44780_driver: Added support for the \e[H and \e[2J escape codes to clear the screen after the i2c_bootloader is done(Tim) Efthimis Kritikos2024-02-11 04:35:44 +0000
a8c29aff9bI2C_BOOTLOADER: Several fixes and a 4.5x performance increase as well as the addition of 16bit reads from the I2C_driver(Tim) Efthimis Kritikos2024-02-10 19:42:18 +0000
be402aa8f7Project: updated copyright notices and README and fixed a few spelling mistakes(Tim) Efthimis Kritikos2024-02-10 15:52:13 +0000
1966ab78b4Peripherals/I2C: Added a CPU I2C driver and wrote a bootloader that uses that to boot from an I2C eeprom(Tim) Efthimis Kritikos2024-02-09 23:28:21 +0000
1d9be44c5aBuild system: renamed upload to upload_bitstream to allow for an upload_firmware in the future(Tim) Efthimis Kritikos2024-01-22 20:19:14 +0000
8281c9a21fFPGA_Board/OrangeCrab_r0.2.1: Switched the GPIO 0/1 pins for I2C to the dedicated ones(Tim) Efthimis Kritikos2023-12-10 04:37:07 +0000
3e66336456Build system: Small fixes and corrected rebuild when only the verilator testbench was changed(Tim) Efthimis Kritikos2023-12-09 02:39:14 +0000
65dfd21ef0Peripherals/I2C_driver: Uncommented code to check for device acknowledgment(Tim) Efthimis Kritikos2023-12-09 00:53:52 +0000
94bc6eba39Build system: Added help text and target mrproper which also deletes downloaded source code(Tim) Efthimis Kritikos2023-12-08 22:10:11 +0000
8544764612Build system: Minor improvement and addition of license notice to one of the files(Tim) Efthimis Kritikos2023-12-07 19:21:31 +0000
bc1dcacfc0Build system: Fixed a bug with building the boot_code/ directory with a lot of make jobs(Tim) Efthimis Kritikos2023-12-07 18:44:31 +0000
533f346f9bBuild system: Added the ability to simulate an FPGA SoC and fixed all the warning verilator gave of the code previously used only for synthesis.(Tim) Efthimis Kritikos2023-12-07 16:39:04 +0000
b1108e375dBuild system: Fixed standalone ./system/Makefile build and general Makefile improvements(Tim) Efthimis Kritikos2023-12-06 18:12:57 +0000
df5b9c13eaProject: Removed some unused verilator warning restrictions and a TODO comment(Tim) Efthimis Kritikos2023-12-06 02:46:39 +0000
05343864daBuild system: Added a script that uses docker to test building the project on some popular linux distros(Tim) Efthimis Kritikos2023-12-06 01:22:07 +0000
8edafd70cfBuild system: Improved the handling of seeds, moved most of the board specific build instructions to the board specific .mk file and fixed bios.asm dependencies(Tim) Efthimis Kritikos2023-12-05 21:46:46 +0000
dc7c4e95f2Boot_code/Brainfuck_compiler: revert accidental increase in the stack size(Tim) Efthimis Kritikos2023-12-05 03:16:21 +0000
acc0581124Boot_code/BIOS: Split the litedram init off to a separate file and included the brainfuck compiler in the bios as a demo for the ram. Also added code to zero out the brainfuck data in the compiler(Tim) Efthimis Kritikos2023-12-05 03:06:59 +0000
2fcc521f12Peripherals/Wishbone_memory: Rewrote the module to be more efficient, smaller and also support byte level addressing. It is correct enough now to run code out of!(Tim) Efthimis Kritikos2023-12-05 02:49:28 +0000
dd1080b42cBuild system: Added maximum CPU frequency to build system info and improved the way nextpnr seed is handled, fixing builds with older versions of make(Tim) Efthimis Kritikos2023-12-05 01:12:17 +0000
26210be950Peripherals/I2C_driver: Corrected the implementation of the bidirectional SDA pin, fixing the final yosys 0.35 warning(Tim) Efthimis Kritikos2023-12-04 22:40:53 +0000
0eecfdcf40Tools/Gen_litedram: Major improvements and cleanup including work in ensuring it is reproducible(Tim) Efthimis Kritikos2023-12-04 21:34:20 +0000
63ea29e399Peripherals/Memory: Added support for the litedram DDR memory controller, created a new memory map and updated all relevant code and files including the addition of rudimentary wait state support for the cpu (BIU)(Tim) Efthimis Kritikos2023-12-03 19:24:12 +0000
f1dc9d8a59Processor/Instructions: Fixed a bug where if IN executed after a microcoded instruction the cpu would go into undefined behavior(Tim) Efthimis Kritikos2023-11-26 00:18:15 +0000
f07e0e7c1fProcessor/Instructions: Added support for the IN <immediate> instruction. Also changed some stuff in system.v to add more devices in the IO/Memory space(Tim) Efthimis Kritikos2023-11-25 04:11:51 +0000
17638d5cbdBuild system: Slight improvements, randomised nextpnr rng seed and printed it to the terminal. In case timing fails running it a bunch of times can yield one value that passes.(Tim) Efthimis Kritikos2023-11-23 23:26:13 +0000
aedefddb5dProject: The cpu finally works perfectly now even at full speed as far as i can tell! I made the ram and register writes synchronous which fixed the weird issues I had, then I added -abc9 to yosys so that nextpnr can actually route the cpu at full speed and increased the display fifo since the cpu is so fast now!!(Tim) Efthimis Kritikos2023-11-15 18:43:03 +0000
98d30a1813Project: removed a .fst.hier file thought to be generated by gtkwave and added the type to gitignore(Tim) Efthimis Kritikos2023-11-15 00:32:40 +0000
09ccce5f30Peripherals/HD44780: Rewrote and cleaned up a lot of the driver code. Unfortunately what i think is a very weird bug in yosys is still affecting the codebase(Tim) Efthimis Kritikos2023-11-15 00:26:46 +0000
0ca1da81b1Assembly code: Fixed a bug where the compiler would print a null byte which was masked by the verilog simulators(Tim) Efthimis Kritikos2023-11-14 21:14:45 +0000
2c8e8a9d9cAdded simple support for \n and \r on the HD44780 driver, increased the synthesised mem to fit brainfuck_compiled.asm and made it the default.(Tim) Efthimis Kritikos2023-11-12 21:39:27 +0000
189b037bdfAdded proper line wrapping for HD44780 LCDs and rewrote half the driver to make it more flexible(Tim) Efthimis Kritikos2023-11-12 17:30:52 +0000
7d2cb5672fReduced numbers to be sorted in gnome_sort.asm to fit in lcd, fixed hlt on real hardware, slowed down cpu, increased lcd fifo and with that I almost got gnome_sort.asm working perfectly on real hardware(Tim) Efthimis Kritikos2023-11-12 07:28:51 +0000
e06c0eeaa0Made the build system simplify the microcode so that yosys understands and synthesises it! Now gnome_sort.asm almost works!(Tim) Efthimis Kritikos2023-11-12 04:04:56 +0000
fa62b07c14Removed probably unnecessary high impedance case yosys was complaining about in registers.v(Tim) Efthimis Kritikos2023-11-12 03:13:22 +0000
f471b305d8Switched some assignments in decode.v to non-blocking which fixed a seemingly unrelated bug with incrementing the accumulator, added some more working test code in colored_led.asm and did some semantic changes as per yosys suggestions(Tim) Efthimis Kritikos2023-11-12 02:54:41 +0000
4c130a8d63Added back removed warnings to verilator since we have now fixed those issues(Tim) Efthimis Kritikos2023-11-12 00:07:33 +0000
a88c420ca5Added an I2C driver, a PCF8574 driver and an HD44780 display driver. Unfortunately this shows that even fibonacci doesn't run correctly. Nonetheless, I made colored_led.asm output text to the display!(Tim) Efthimis Kritikos2023-11-09 22:10:34 +0000
01dcbfa7a1The CPU works on real hardware for the first time! I added an adjustment for ram size, added control for a led and a test program for it. On the fpga board there is an actual led there that I used to verify functionality(Tim) Efthimis Kritikos2023-11-06 08:12:58 +0000
30ffa1b00cFixed a "combinatorial loop" and now if the build-in memory is reduced the design can be synthesized!(Tim) Efthimis Kritikos2023-11-06 05:36:04 +0000
934e2f5a36Fixed a bunch of things wrong with fpga_top.v and gated off some more simulation-only code(Tim) Efthimis Kritikos2023-11-02 23:46:12 +0000
08aac5c7b6Removed some code that wasn't meant for synthesis and fixed important bug in Makefile(Tim) Efthimis Kritikos2023-11-02 22:19:15 +0000
601397b7f0Properly added fpga_top.v stuff in the build system and fixed some syntax errors(Tim) Efthimis Kritikos2023-11-02 22:00:07 +0000
43f3e16ca4Removed all instances of inout since from what i understand it's mostly synthesisable(Tim) Efthimis Kritikos2023-11-02 21:48:12 +0000
36bf8f9c7aAdded OrangeCrab board-specific code to connect the cpu to the outside world(Tim) Efthimis Kritikos2023-11-02 20:40:04 +0000
5feee9de57Added support to the build system for synthesising, place and routing, serialising and uploading the design to a Lattice ECP5 OrangeCrab FPGA(Tim) Efthimis Kritikos2023-11-02 00:29:14 +0000
a693b87e96General cleanup and moved the reading of instruction parameters from a separate stage in execute to circuitry during the decode(Tim) Efthimis Kritikos2023-05-29 02:28:56 +0100
af63ef1d68Moved the decoder logic to decoder.v Now processor.v only connects the different modules(Tim) Efthimis Kritikos2023-05-27 23:35:00 +0100
021dd06e9aAdded support for some more instructions, fixed a bug in CMP and also added a program that uses them(Tim) Efthimis Kritikos2023-05-19 17:59:20 +0100
7db70d79ffMade execute unit start at a state transition of a signal from the decoder thus allowing for an IPC of 0.99 !!(Tim) Efthimis Kritikos2023-05-17 21:28:50 +0100
90f63b525dMade the decode unit able to continuously decode (simple) instructions if BIU allows it(Tim) Efthimis Kritikos2023-05-17 20:07:45 +0100
30c3deca37Made the execute unit signal the end of execution by a state change rather than the state of a signal to allow for one cycle instructions(Tim) Efthimis Kritikos2023-05-17 11:05:20 +0100
53e9d371d7Fully optimised BIU. Now it can instantly deliver instructions back to back(Tim) Efthimis Kritikos2023-05-16 18:07:28 +0100
(Tim) Efthimis Kritikos