Cleaned the decoder a bit and laid down some of the groundwork for microcode
This commit is contained in:
parent
e6c9c722e3
commit
e2e9a92832
1
Makefile
1
Makefile
@ -19,6 +19,7 @@
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SYSTEM_VVP=system/system.vvp
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BOOT_CODE=boot_code/brainfuck.txt
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GTKWSAVE=./gtkwave_savefile.gtkw
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MICROCODE=system/ucode.hex
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include common.mk
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@ -11,6 +11,7 @@ A CPU that aims to be binary compatible with the 8086 and with as many optimisat
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* [ ] Is pipelined
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* [ ] Is Out of Order
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* [ ] Is superscalar
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* [ ] Has been successfully synthesized
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### Simulating it
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To simulate this project you need Icarus Verilog, bin86, GNU make, xxd and the posix coreutils.
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@ -34,13 +34,13 @@ disas: $(subst .txt,.disas,${BOOT_CODE})
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# Running simulation
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%.lx2 %.memdump: %.txt ${SYSTEM_VVP}
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${QUIET_VVP}
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${Q}vvp "${SYSTEM_VVP}" -lxt2 +BOOT_CODE="$<" +WAVEFORM="$(subst .txt,.lx2,$<)" +MEMDUMP="$(subst .txt,.memdumptxt,$<)"
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${Q}vvp "${SYSTEM_VVP}" -lxt2 +BOOT_CODE="$<" +WAVEFORM="$(subst .txt,.lx2,$<)" +MEMDUMP="$(subst .txt,.memdumptxt,$<)" +MICROCODE="${MICROCODE}"
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${Q}grep -v '^//' "$(subst .txt,.memdumptxt,$<)" | xxd -ps -c 2 -r > "$(subst .txt,.memdump,$<)"
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${Q}rm "$(subst .txt,.memdumptxt,$<)"
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%.run: %.txt ${SYSTEM_VVP}
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${QUIET_VVP}
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${Q}vvp -i "${SYSTEM_VVP}" +BOOT_CODE="$<"
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${Q}vvp -i "${SYSTEM_VVP}" +BOOT_CODE="$<" +MICROCODE="${MICROCODE}"
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%.disas: %.bin
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objdump -D -b binary -m i8086 $^ | less
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@ -16,10 +16,11 @@
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# along with this program. If not, see <http://www.gnu.org/licenses/>.
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#
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SOURCES=processor.v testbench.v memory.v registers.v alu.v decoder.v general.v
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INCLUDES=proc_state_def.v alu_header.v config.v
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INCLUDES=proc_state_def.v alu_header.v config.v ucode_header.v ucode.hex
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SYSTEM_VVP=system.vvp
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BOOT_CODE=boot_code.txt
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GTKWSAVE=../gtkwave_savefile.gtkw
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MICROCODE=ucode.hex
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include ../common.mk
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415
system/decoder.v
415
system/decoder.v
@ -19,7 +19,28 @@
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`include "proc_state_def.v"
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`include "alu_header.v"
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`include "ucode_header.v"
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module microcode(
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input [`UCODE_ADDR_BITS-1:0] ADDR,
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output [`UCODE_DATA_BITS-1:0] DATA
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);
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initial begin
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string ucode_path;
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if($value$plusargs("MICROCODE=%s",ucode_path))begin
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$readmemb(ucode_path,ucode,0,`UCODE_SIZE-1);
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end else begin
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$display("Please supply microcode rom file as a runtime vvp argument +MICROCODE=<path>");
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$finish;
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end
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end
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reg [`UCODE_DATA_BITS-1:0] ucode [ 0:`UCODE_SIZE-1 ];
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assign DATA=ucode[ADDR];
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endmodule
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module decoder(
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input wire [15:0] CIR,input wire [15:0] FLAGS, output reg Wbit, output reg Sbit, output reg unaligning ,output reg opcode_size, output reg ERROR,output reg [`PROC_STATE_BITS-1:0]next_state
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@ -29,6 +50,10 @@ module decoder(
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,output reg [2:0]ALU_1OP
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);
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wire [`UCODE_DATA_BITS-1:0] ucode_data;
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reg [`UCODE_ADDR_BITS-1:0] UCODE_ADDR;
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microcode ucode(UCODE_ADDR,ucode_data);
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/* 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 */
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`define invalid_instruction next_state=`PROC_IF_STATE_ENTRY;ERROR=1;MOD=2'b11;
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@ -38,94 +63,79 @@ module decoder(
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always @( CIR ) begin
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ERROR=0;HALT=0;
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case(CIR[15:10])
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6'b000001 : begin
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/* ADD, ... */
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if ( CIR[9:9] == 0 )begin
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/* Add Immediate word/byte to accumulator */
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/* 0 0 0 0 0 1 0 W | DATA | DATA if W |*/
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opcode_size=0;
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has_operands=1;
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Wbit=CIR[8:8];
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if(Wbit)
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`start_unaligning_instruction
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else
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`start_aligning_instruction
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MOD=2'b11;
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casex({CIR[15:8],CIR[5:3]})
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11'b0000_010x_xxx : begin
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/* Add Immediate word/byte to accumulator */
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/* 0 0 0 0 0 1 0 W | DATA | DATA if W |*/
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opcode_size=0;
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has_operands=1;
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Wbit=CIR[8:8];
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if(Wbit)
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`start_unaligning_instruction
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else
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`start_aligning_instruction
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MOD=2'b11;
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in_alu1_sel1=2'b00;
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in_alu1_sel2=2'b01;
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out_alu1_sel=3'b011;
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reg_read_port1_addr={Wbit,3'b000};
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reg_write_addr={Wbit,3'b000};
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ALU_1OP=`ALU_OP_ADD;
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if(Wbit==1)
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next_state=`PROC_DE_LOAD_16_PARAM;
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else begin
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PARAM1[7:0]=CIR[7:0];
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next_state=`PROC_EX_STATE_ENTRY;
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end
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end
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11'b1000_00xx_000 : begin
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/* Add Immediate word/byte to register/memory */
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/* 1 0 0 0 0 0 S W | MOD 0 0 0 R/M | < DISP LO > | < DISP HI > | DATA | DATA if W | */
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`start_aligning_instruction
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opcode_size=1;
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has_operands=1;
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Wbit=CIR[8:8];
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Sbit=CIR[9:9];
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MOD=2'b11;
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in_alu1_sel1=2'b00;
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in_alu1_sel2=2'b01;
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out_alu1_sel={1'b0,MOD};
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reg_read_port1_addr={Wbit,RM};
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reg_write_addr={Wbit,RM};
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ALU_1OP=`ALU_OP_ADD;
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next_state=`PROC_DE_LOAD_16_PARAM;
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if(Wbit==1)
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next_state=`PROC_DE_LOAD_16_PARAM;
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else begin
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`invalid_instruction /*do 8bit loads*/
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end
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end
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11'b1000_00xx_111 : begin
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/* CMP - compare Immediate with register / memory */
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/* 1 0 0 0 0 0 S W | MOD 1 1 1 R/M | < DISP LO > | < DISP HI > | DATA | DATA if W | */
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opcode_size=1;
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has_operands=1;
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Wbit=CIR[8:8];
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Sbit=CIR[9:9];
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MOD=CIR[7:6];
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RM=CIR[2:0];
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if(((Wbit==1)&&(Sbit==1))||Wbit==0)begin
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`start_unaligning_instruction
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end else begin
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`invalid_instruction;
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end
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if(MOD==2'b11)begin
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in_alu1_sel1=2'b00;
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in_alu1_sel2=2'b01;
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out_alu1_sel=3'b011;
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reg_read_port1_addr={Wbit,3'b000};
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reg_write_addr={Wbit,3'b000};
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ALU_1OP=`ALU_OP_ADD;
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if(Wbit==1)
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next_state=`PROC_DE_LOAD_16_PARAM;
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else begin
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PARAM1[7:0]=CIR[7:0];
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next_state=`PROC_EX_STATE_ENTRY;
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end
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reg_read_port1_addr={Wbit,RM};
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out_alu1_sel=3'b100;
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ALU_1OP=`ALU_OP_SUB;
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next_state=`PROC_DE_LOAD_8_PARAM;
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end else begin
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`invalid_instruction
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end
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end
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6'b100000 : begin
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/* ADD, ADC, SUB, SBB, CMP , AND, ... */
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case (CIR[5:3])
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3'b000 : begin
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/* Add Immediate word/byte to register/memory */
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/* 1 0 0 0 0 0 S W | MOD 0 0 0 R/M | < DISP LO > | < DISP HI > | DATA | DATA if W | */
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`start_aligning_instruction
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opcode_size=1;
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has_operands=1;
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Wbit=CIR[8:8];
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Sbit=CIR[9:9];
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MOD=2'b11;
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in_alu1_sel1=2'b00;
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in_alu1_sel2=2'b01;
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out_alu1_sel={1'b0,MOD};
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reg_read_port1_addr={Wbit,RM};
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reg_write_addr={Wbit,RM};
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ALU_1OP=`ALU_OP_ADD;
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next_state=`PROC_DE_LOAD_16_PARAM;
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if(Wbit==1)
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next_state=`PROC_DE_LOAD_16_PARAM;
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else begin
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`invalid_instruction /*do 8bit loads*/
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end
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end
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3'b111 : begin
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/* CMP - compare Immediate with register / memory */
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/* 1 0 0 0 0 0 S W | MOD 1 1 1 R/M | < DISP LO > | < DISP HI > | DATA | DATA if W | */
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opcode_size=1;
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has_operands=1;
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Wbit=CIR[8:8];
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Sbit=CIR[9:9];
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MOD=CIR[7:6];
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RM=CIR[2:0];
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if(((Wbit==1)&&(Sbit==1))||Wbit==0)begin
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`start_unaligning_instruction
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end else begin
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`invalid_instruction;
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end
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if(MOD==2'b11)begin
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in_alu1_sel1=2'b00;
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in_alu1_sel2=2'b01;
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reg_read_port1_addr={Wbit,RM};
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out_alu1_sel=3'b100;
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ALU_1OP=`ALU_OP_SUB;
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next_state=`PROC_DE_LOAD_8_PARAM;
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end else begin
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`invalid_instruction
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end
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end
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default:begin
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`invalid_instruction
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end
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endcase
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end
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6'b101100,
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6'b101101:begin
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11'b1011_0xxx_xxx : begin
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/* MOV - Move Immediate byte to register */
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/* 1 0 1 1 W REG | DATA | DATA if W |*/
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`start_aligning_instruction
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@ -142,8 +152,7 @@ always @( CIR ) begin
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ALU_1OP=`ALU_OP_ADD;
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next_state=`PROC_EX_STATE_ENTRY;
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end
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6'b101110,
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6'b101111 : begin
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11'b1011_1xxx_xxx : begin
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/*MOV - Move Immediate word to register*/
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`start_unaligning_instruction
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has_operands=1;
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@ -159,7 +168,7 @@ always @( CIR ) begin
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next_state=`PROC_DE_LOAD_16_PARAM;
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end
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6'b100010 : begin
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11'b1000_10xx_xxx : begin
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/* MOV - Reg/Mem to/from register */
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/* 1 0 0 0 1 0 D W | MOD REG RM | < DISP LO > | < DISP HI > |*/
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has_operands=0;
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@ -204,10 +213,7 @@ always @( CIR ) begin
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ALU_1OP=`ALU_OP_ADD;
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PARAM2=0;
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end
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6'b010000,//INC
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6'b010001,//INC
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6'b010010,//DEC
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6'b010011:begin//DEC
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11'b0100_xxxx_xxx:begin//DEC
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/* DEC - Decrement Register */
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/* | 0 1 0 0 1 REG | */
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/* INC - Increment Register */
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@ -229,97 +235,69 @@ always @( CIR ) begin
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ALU_1OP=`ALU_OP_SUB;
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next_state=`PROC_EX_STATE_ENTRY;
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end
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6'b111111 : begin
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/* INC */
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if (CIR[9:9] == 1 ) begin
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case (CIR[5:3])
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3'b000,3'b001 :begin
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/* INC - Register/Memory */
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/* 1 1 1 1 1 1 1 W | MOD 0 0 0 R/M | < DISP LO> | < DISP HI> */
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/* DEC - Register/Memory */
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/* 1 1 1 1 1 1 1 W | MOD 0 0 1 R/M | < DISP LO> | < DISP HI> */
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has_operands=1;
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opcode_size=1;
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`start_aligning_instruction
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Wbit=CIR[8:8];
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MOD=CIR[7:6];
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RM=CIR[2:0];
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in_alu1_sel1=(MOD==2'b11)? 2'b01 : 2'b00;
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in_alu1_sel2=2'b00;/* number 1 */
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PARAM2=1;
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out_alu1_sel={1'b0,MOD};
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11'b1111_111x_00x : begin
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/* INC - Register/Memory */
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/* 1 1 1 1 1 1 1 W | MOD 0 0 0 R/M | < DISP LO> | < DISP HI> */
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/* DEC - Register/Memory */
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/* 1 1 1 1 1 1 1 W | MOD 0 0 1 R/M | < DISP LO> | < DISP HI> */
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has_operands=1;
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opcode_size=1;
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`start_aligning_instruction
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Wbit=CIR[8:8];
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MOD=CIR[7:6];
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RM=CIR[2:0];
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in_alu1_sel1=(MOD==2'b11)? 2'b01 : 2'b00;
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in_alu1_sel2=2'b00;/* number 1 */
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PARAM2=1;
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out_alu1_sel={1'b0,MOD};
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/*in case MOD=11 */
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reg_read_port1_addr={1'b0,RM};
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reg_write_addr={1'b0,RM};
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/*in case MOD=11 */
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reg_read_port1_addr={1'b0,RM};
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reg_write_addr={1'b0,RM};
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ALU_1OP=(CIR[3:3]==1)?`ALU_OP_SUB:`ALU_OP_ADD;
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if ( MOD == 2'b11 )
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next_state=`PROC_EX_STATE_ENTRY;
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else
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next_state=`RPOC_MEMIO_READ;
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end
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default:begin
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`invalid_instruction
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end
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endcase
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end else begin
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`invalid_instruction
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ALU_1OP=(CIR[3:3]==1)?`ALU_OP_SUB:`ALU_OP_ADD;
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if ( MOD == 2'b11 )
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next_state=`PROC_EX_STATE_ENTRY;
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else
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next_state=`RPOC_MEMIO_READ;
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end
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11'b1111_0100_xxx : begin
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/* HLT - Halt */
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/* 1 1 1 1 0 1 0 0 | */
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has_operands=0;
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opcode_size=0;
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`start_unaligning_instruction
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MOD=2'b11;
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HALT=1;
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next_state=`PROC_HALT_STATE;
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end
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11'b0011_110x_xxx : begin
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/* CMP - Compare Immediate with accumulator */
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/* 0 0 1 1 1 1 0 W | DATA | DATA if W |*/
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/* */
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/* NOTE: 8086 doc doesn't show the third byte but the */
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/* W flag and my assembler seem to disagree */
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Wbit=CIR[8:8];
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opcode_size=0;
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has_operands=1;
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if(Wbit)
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`start_unaligning_instruction
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else
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`start_aligning_instruction
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MOD=2'b11;
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in_alu1_sel1=2'b00;
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in_alu1_sel2=2'b01;
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reg_read_port1_addr={Wbit,3'b000};
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out_alu1_sel=3'b100;
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ALU_1OP=`ALU_OP_SUB;
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if(Wbit==1)
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next_state=`PROC_DE_LOAD_16_PARAM;
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else begin
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PARAM1[7:0]=CIR[7:0];
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next_state=`PROC_EX_STATE_ENTRY;
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end
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end
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6'b111101 : begin
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/*HLT, CMC, TEST, NOT, NEG, MUL, IMUL, .... */
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case (CIR[9:8])
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2'b00:begin
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/* HLT - Halt */
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/* 1 1 1 1 0 1 0 0 | */
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has_operands=0;
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opcode_size=0;
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`start_unaligning_instruction
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MOD=2'b11;
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HALT=1;
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next_state=`PROC_HALT_STATE;
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end
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default:begin
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`invalid_instruction;
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end
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endcase
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end
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6'b001111 : begin
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if ( CIR[9:9] == 0 ) begin
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/* CMP - Compare Immediate with accumulator */
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/* 0 0 1 1 1 1 0 W | DATA | DATA if W |*/
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/* */
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/* NOTE: 8086 doc doesn't show the third byte but the */
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/* W flag and my assembler seem to disagree */
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Wbit=CIR[8:8];
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opcode_size=0;
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has_operands=1;
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if(Wbit)
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`start_unaligning_instruction
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else
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`start_aligning_instruction
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MOD=2'b11;
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in_alu1_sel1=2'b00;
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in_alu1_sel2=2'b01;
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reg_read_port1_addr={Wbit,3'b000};
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out_alu1_sel=3'b100;
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ALU_1OP=`ALU_OP_SUB;
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if(Wbit==1)
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next_state=`PROC_DE_LOAD_16_PARAM;
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else begin
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PARAM1[7:0]=CIR[7:0];
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next_state=`PROC_EX_STATE_ENTRY;
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end
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end else begin
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`invalid_instruction
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end
|
||||
end
|
||||
6'b011100,
|
||||
6'b011101,
|
||||
6'b011110,
|
||||
6'b011111:begin
|
||||
11'b0111_xxxx_xxx:begin
|
||||
/* Conditional relative jumps */
|
||||
/* JE/JZ - Jump on Zero */
|
||||
/* 0 1 1 1 0 1 0 0 | IP-INC8 |*/
|
||||
@ -372,68 +350,31 @@ always @( CIR ) begin
|
||||
end
|
||||
endcase
|
||||
end
|
||||
6'b111010:begin
|
||||
/* JMP,CALL */
|
||||
case(CIR[9:8])
|
||||
2'b00: begin
|
||||
/* CALL - Call direct within segment */
|
||||
/* 1 1 1 0 1 0 0 0 | IP-INC-LO | IP-INC-HI |*/
|
||||
`invalid_instruction
|
||||
end
|
||||
2'b01: begin
|
||||
/* JMP - Unconditional Jump direct within segment */
|
||||
/* 1 1 1 0 1 0 0 1 | IP-INC-LO | IP-INC-HI |*/
|
||||
`invalid_instruction
|
||||
end
|
||||
2'b10: begin
|
||||
/* JMP - Unconditional jump direct intersegment */
|
||||
/* 0 0 0 0 0 0 0 0 | IP-LO | IP-HI | CS-LO | CS-HI | */
|
||||
`invalid_instruction
|
||||
end
|
||||
2'b11: begin
|
||||
/* JMP - Unconditional jump direct within segment (short) */
|
||||
/* | 1 1 1 0 1 0 0 1 | IP-INC-LO | */
|
||||
`start_aligning_instruction
|
||||
opcode_size=0;
|
||||
has_operands=1;
|
||||
Wbit=1;
|
||||
in_alu1_sel1=2'b10;
|
||||
in_alu1_sel2=2'b00;
|
||||
PARAM2={{8{CIR[7:7]}},CIR[7:0]};
|
||||
ALU_1OP=`ALU_OP_ADD_SIGNED_B;
|
||||
out_alu1_sel=3'b101;
|
||||
next_state=`PROC_EX_STATE_ENTRY;
|
||||
end
|
||||
endcase
|
||||
11'b1110_1011_xxx:begin
|
||||
/* JMP - Unconditional jump direct within segment (short) */
|
||||
/* | 1 1 1 0 1 0 1 1 | IP-INC-LO | */
|
||||
`start_aligning_instruction
|
||||
opcode_size=0;
|
||||
has_operands=1;
|
||||
Wbit=1;
|
||||
in_alu1_sel1=2'b10;
|
||||
in_alu1_sel2=2'b00;
|
||||
PARAM2={{8{CIR[7:7]}},CIR[7:0]};
|
||||
ALU_1OP=`ALU_OP_ADD_SIGNED_B;
|
||||
out_alu1_sel=3'b101;
|
||||
next_state=`PROC_EX_STATE_ENTRY;
|
||||
end
|
||||
6'b110011:begin
|
||||
case(CIR[9:8])
|
||||
2'b00:begin
|
||||
`invalid_instruction
|
||||
end
|
||||
2'b01:begin
|
||||
if(CIR[7:0]==8'h21) begin
|
||||
/* INT - execute interrupt handler */
|
||||
/* 1 1 0 0 1 1 0 1 | DATA |*/
|
||||
has_operands=1;
|
||||
opcode_size=0;
|
||||
`start_aligning_instruction
|
||||
/* Emulate MS-DOS print routines */
|
||||
if(register_file.registers[0][15:8]==8'h02)begin
|
||||
$write("%s" ,register_file.registers[2][7:0]); /*TODO:Could trigger erroneously while CIR is not final*/
|
||||
end
|
||||
next_state=`PROC_IF_STATE_ENTRY;
|
||||
end else begin
|
||||
`invalid_instruction
|
||||
end
|
||||
end
|
||||
2'b10:begin
|
||||
`invalid_instruction
|
||||
end
|
||||
2'b11:begin
|
||||
`invalid_instruction
|
||||
end
|
||||
endcase
|
||||
11'b1100_1101_xxx:begin
|
||||
/* INT - execute interrupt handler */
|
||||
/* 1 1 0 0 1 1 0 1 | DATA |*/
|
||||
has_operands=1;
|
||||
opcode_size=0;
|
||||
`start_aligning_instruction
|
||||
/* Emulate MS-DOS print routines */
|
||||
if(CIR[7:0]==8'h21 && register_file.registers[0][15:8]==8'h02)begin
|
||||
$write("%s" ,register_file.registers[2][7:0]); /*TODO:Could trigger erroneously while CIR is not final*/
|
||||
end
|
||||
next_state=`PROC_IF_STATE_ENTRY;
|
||||
end
|
||||
default:begin
|
||||
`invalid_instruction
|
||||
|
||||
9
system/ucode.hex
Normal file
9
system/ucode.hex
Normal file
@ -0,0 +1,9 @@
|
||||
|
||||
//s : Opcode size 0:8bit 1:16bit
|
||||
//h : Has operands as part of the instruction: 0: No 1: Yes
|
||||
|
||||
// |sh
|
||||
@000 01_11
|
||||
@001 11_10
|
||||
@002 1000
|
||||
@003 0010
|
||||
6
system/ucode_header.v
Normal file
6
system/ucode_header.v
Normal file
@ -0,0 +1,6 @@
|
||||
`define UCODE_ADDR_BITS 9
|
||||
`define UCODE_DATA_BITS 32
|
||||
`define UCODE_SIZE 4
|
||||
|
||||
`define ADD_AL_IB 0
|
||||
`define ADD_AX_IW 1
|
||||
Loading…
Reference in New Issue
Block a user