Efthimis/9086
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A CPU that aims to be binary compatible with the 8086 ISA, focused on optimisation and flexibility.
83 Commits 2 Branches 4 Tags 1.8 MiB
Verilog 66.9%
Makefile 9.9%
Assembly 9.4%
Shell 6.9%
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(Tim) Efthimis Kritikos 82baacfd5b Fixed race condition giving garbage data on debug register write prints and ordering of reg write and instr fetch debug prints
2023-03-12 08:55:40 +00:00
boot_code Added the OUT instruction to be able to properly address I/O and moved printing logic to a device on the I/O space. Also added IRET which is basically just a RET in this case 2023-03-09 06:03:13 +00:00
readme_files Fixed register addressing bug, mem read endianness, cleaned up code and added a provisional project logo 2023-02-19 00:20:53 +00:00
system Fixed race condition giving garbage data on debug register write prints and ordering of reg write and instr fetch debug prints 2023-03-12 08:55:40 +00:00
.gitignore Wrote a more complete testbench for verilator, switched from lx2 to fst and fixed cpu clock frequency calculation 2023-03-05 00:10:55 +00:00
8086_documentation.md Overhauled cpu frontend. Made memory byte addressable (necessary), cleaned up state machine and fixed small bug with MOV 2023-03-03 06:29:06 +00:00
common.mk Added partial support for the software interrupt INT instruction 2023-03-08 07:26:28 +00:00
COPYING Properly licensed the project and run it through aspell 2023-02-13 16:49:17 +00:00
gtkwave_savefile.gtkw Added the OUT instruction to be able to properly address I/O and moved printing logic to a device on the I/O space. Also added IRET which is basically just a RET in this case 2023-03-09 06:03:13 +00:00
Makefile Added the OUT instruction to be able to properly address I/O and moved printing logic to a device on the I/O space. Also added IRET which is basically just a RET in this case 2023-03-09 06:03:13 +00:00
README.md Slight adjustment to README 2023-03-06 21:57:36 +00:00

README.md

9086 logo

A CPU that aims to be binary compatible with the 8086 and with as many optimisations as possible

Progress

  • Executing code
  • Is Turing complete
  • Can boot up MS-DOS / FreeDOS
  • Is completely binary compatible
  • Is pipelined
  • Is Out of Order
  • Is superscalar
  • Has been successfully synthesized

Simulating it

Both Verilator and Icarus Verilog can be used for simulation. You can select which one you want with the SIM variable on common.mk Specifically this list shows the software needed and the versions used during development (other versions should work as well)

  • Icarus Verilog : version 11.0 OR (preferred) Verilator : 5.006
  • bin86 : 0.16.21
  • GNU Make : 4.4.1
  • xxd : 2022-01-14
  • POSIX coreutils : GNU coreutils 9.1

After that you can run make on the top level directory and it should build everything and start the simulation

License

All parts of this project are licensed under the GNU General Public License version 3 or later