Efthimis/9086
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A CPU that aims to be binary compatible with the 8086 ISA, focused on optimisation and flexibility.
49 Commits 2 Branches 4 Tags 1.8 MiB
Verilog 66.9%
Makefile 9.9%
Assembly 9.4%
Shell 6.9%
Brainfuck 5.9%
Other 1%
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(Tim) Efthimis Kritikos 619702384b Wrote an optimised native brainfuck compiler intended to be the default program running on release v0.1 utilising a good precentage of the 8086 instruction set
2023-02-19 21:42:59 +00:00
boot_code Wrote an optimised native brainfuck compiler intended to be the default program running on release v0.1 utilising a good precentage of the 8086 instruction set 2023-02-19 21:42:59 +00:00
readme_files Fixed register addressing bug, mem read endianness, cleaned up code and added a provisional project logo 2023-02-19 00:20:53 +00:00
system Cleaned the decoder a bit and laid down some of the groundwork for microcode 2023-02-19 16:22:23 +00:00
.gitignore Wrote an optimised native brainfuck compiler intended to be the default program running on release v0.1 utilising a good precentage of the 8086 instruction set 2023-02-19 21:42:59 +00:00
8086_documentation.md Run the project through aspell and tweaked the README 2023-02-19 00:52:52 +00:00
common.mk Cleaned the decoder a bit and laid down some of the groundwork for microcode 2023-02-19 16:22:23 +00:00
COPYING Properly licensed the project and run it through aspell 2023-02-13 16:49:17 +00:00
gtkwave_savefile.gtkw Improved build system and project directory structure 2023-02-16 01:52:02 +00:00
Makefile Cleaned the decoder a bit and laid down some of the groundwork for microcode 2023-02-19 16:22:23 +00:00
README.md Cleaned the decoder a bit and laid down some of the groundwork for microcode 2023-02-19 16:22:23 +00:00

README.md

9086 logo

A CPU that aims to be binary compatible with the 8086 and with as many optimisations as possible

Progress

  • Executing code
  • Is Turing complete
  • Can boot up MS-DOS / FreeDOS
  • Is completely binary compatible
  • Is pipelined
  • Is Out of Order
  • Is superscalar
  • Has been successfully synthesized

Simulating it

To simulate this project you need Icarus Verilog, bin86, GNU make, xxd and the posix coreutils. After that you can run make on the top level directory and it should build everything and start the simulation

At the time of development the versions used are :

  • Icarus Verilog version 11.0 (stable)
  • bin86 version: 0.16.17
  • GNU Make 4.3
  • xxd 2022-01-14
  • GNU coreutils 8.32

License

All parts of this project are licensed under the GNU General Public License version 3 or later