Added support for writing to memory
This commit is contained in:
parent
7c1067088c
commit
037f6dd7da
1
.gitignore
vendored
1
.gitignore
vendored
@ -8,3 +8,4 @@ cpu/boot_code.txt
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cpu/brainfuck.bin
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cpu/brainfuck.txt
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cpu/memdump.txt
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cpu/memdump.bin
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@ -22,6 +22,7 @@ VVP=processor.vvp
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.PHONY: brainf
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brainf: ${VVP} brainfuck.txt
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vvp ${VVP} +BOOT_CODE=brainfuck.txt
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grep -v '^//' memdump.txt | xxd -ps -c 2 -r > memdump.bin
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.PHONY: run
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run: ${VVP} boot_code.txt
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@ -34,6 +35,7 @@ build: ${VVP}
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wave: ${VVP} brainfuck.txt
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vvp ${VVP} -lxt2 +BOOT_CODE=brainfuck.txt
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gtkwave test.lx2 gtkwave_savefile.gtkw
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grep -v '^//' memdump.txt | xxd -ps -c 2 -r > memdump.bin
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${VVP} : ${SOURCES} ${INCLUDES}
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iverilog -g2012 ${SOURCES} -o $@
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@ -1,15 +1,15 @@
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[*]
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[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
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[*] Fri Feb 10 01:43:01 2023
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[*] Tue Feb 14 12:39:46 2023
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[*]
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[dumpfile] "/home/user/UNI_DATA/COMS30046_2022_TB-2/projects/9086/cpu/test.lx2"
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[dumpfile_mtime] "Fri Feb 10 01:42:12 2023"
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[dumpfile_size] 1058
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[dumpfile_mtime] "Tue Feb 14 12:37:32 2023"
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[dumpfile_size] 1922
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[savefile] "/home/user/UNI_DATA/COMS30046_2022_TB-2/projects/9086/cpu/gtkwave_savefile.gtkw"
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[timestart] 0
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[size] 1438 1059
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[pos] -1 -1
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*-21.795050 6163000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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*-23.795050 41712000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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[treeopen] tb.
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[treeopen] tb.p.
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[sst_width] 221
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@ -19,18 +19,17 @@
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@28
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tb.p.clock[0]
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tb.p.reset[0]
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tb.p.state[3:0]
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tb.p.state[4:0]
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@22
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tb.p.external_address_bus[19:0]
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tb.p.external_data_bus[15:0]
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tb.p.CIR[15:0]
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@28
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tb.p.EXCEPTION[0]
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@22
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tb.p.ADDER16_1.A[15:0]
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tb.p.ADDER16_1.B[15:0]
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tb.p.ADDER16_1.OUT[15:0]
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tb.p.PARAM1[15:0]
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tb.p.PARAM2[15:0]
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@29
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tb.p.reg_write[0]
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tb.p.read[0]
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@28
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tb.p.write[0]
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tb.p.ERROR[0]
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[pattern_trace] 1
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[pattern_trace] 0
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@ -17,7 +17,7 @@
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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module rom(input [19:0] address,output wire [15:0] data ,input rd,input cs);
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module mem(input [19:0] address,inout wire [15:0] data ,input rd,input wr,input cs);
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reg [15:0] memory [0:599];
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initial begin
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string boot_code;
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@ -25,5 +25,11 @@ initial begin
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boot_code="boot_code.txt";
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$readmemh(boot_code, memory);
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end
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assign data = !rd & !cs ? memory[address]: 'hz;
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always @(negedge wr) begin
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memory[address]=data;
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end
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endmodule
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@ -18,26 +18,39 @@
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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`define PROC_HALT_STATE 4'b0000
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`define PROC_STATE_BITS 5
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`define PROC_HALT_STATE 5'b00000
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/*INSTRUCTION FETCH STATE*/
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`define PROC_IF_STATE_ENTRY 4'b0001
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`define PROC_IF_WRITE_CIR 4'b0010
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`define PROC_IF_STATE_EXTRA_FETCH_SET 4'b0011
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`define PROC_IF_STATE_EXTRA_FETCH 4'b1111 /******/
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`define PROC_IF_STATE_ENTRY 5'b00001
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`define PROC_IF_WRITE_CIR 5'b00010
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`define PROC_IF_STATE_EXTRA_FETCH_SET 5'b00011
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`define PROC_IF_STATE_EXTRA_FETCH 5'b00100
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/*DECODE SATE*/
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`define PROC_DE_STATE_ENTRY 4'b0100
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`define PROC_DE_LOAD_16_PARAM 4'b0101
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`define PROC_DE_LOAD_16_EXTRA_FETCH_SET 4'b0110
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`define PROC_DE_LOAD_16_EXTRA_FETCH 4'b0111
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`define PROC_DE_STATE_ENTRY 5'b01000
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`define PROC_DE_LOAD_16_PARAM 5'b01001
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`define PROC_DE_LOAD_16_EXTRA_FETCH_SET 5'b01010
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`define PROC_DE_LOAD_16_EXTRA_FETCH 5'b01011
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/*MEM/IO READ*/
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`define RPOC_MEMIO_READ 4'b1100
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`define PROC_MEMIO_SETADDR 4'b1101
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`define PROC_MEMIO_GET_ALIGNED_DATA 4'b1110 /* :) */
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`define PROC_MEMIO_GET_UNALIGNED_DATA 4'b1010 /* :( */
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`define RPOC_MEMIO_READ 5'b10000
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`define PROC_MEMIO_READ_SETADDR 5'b10001
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`define PROC_MEMIO_GET_ALIGNED_DATA 5'b10010 /* :) */
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`define PROC_MEMIO_GET_UNALIGNED_DATA 5'b10011 /* :( */
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/*EXECUTE STATE*/
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`define PROC_EX_STATE_ENTRY 4'b1000
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`define PROC_EX_STATE_EXIT 4'b1001
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`define PROC_EX_STATE_ENTRY 5'b11000
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`define PROC_EX_STATE_EXIT 5'b11001
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/*MEM/IO WRITE*/
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`define PROC_MEMIO_WRITE 5'b10100
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//`define PROC_MEMIO_WRITE_SETADDR 5'b10101
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`define PROC_MEMIO_PUT_ALIGNED_DATA 5'b10101
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`define PROC_MEMIO_PUT_UNALIGNED_DATA 5'b10110
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`define PROC_MEMIO_PUT_BYTE 5'b10111
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`define PROC_MEMIO_PUT_BYTE_STOP_READ 5'b11110 /****/
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`define PROC_MEMIO_PUT_BYTE_WRITE 5'b11111 /****/
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133
cpu/processor.v
133
cpu/processor.v
@ -34,9 +34,13 @@ endmodule
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module processor ( input clock, input reset, output reg [19:0] external_address_bus, inout [15:0] external_data_bus,output reg read, output reg write, output reg HALT,output reg ERROR);
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/*if we don't read, output the register to have the bus stable by the write falling edge*/
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reg [15:0] data_bus_output_register;
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assign external_data_bus=read?data_bus_output_register:'hz;
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/*** Global Definitions ***/
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// State
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reg [3:0] state;
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reg [`PROC_STATE_BITS-1:0] state;
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// Registers
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reg [19:0] ProgCount;
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@ -44,8 +48,8 @@ reg [15:0] CIR;
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reg [15:0] PARAM1;
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reg [15:0] PARAM2;
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reg unaligned_access;
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reg [1:0]IN_MOD;
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reg [2:0]IN_RM;
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reg [1:0]MOD;
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reg [2:0]RM;
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reg Wbit;
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reg [15:0]FLAGS;
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/* . . . . O D I T S Z . A . P . C */
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@ -69,6 +73,7 @@ reg [15:0]FLAGS;
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// D - Direction flag : 1: string instructions decrement 0: they increment
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//
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// O - Overflow flag : set on arithmetic overflow
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reg [15:0] BYTE_WRITE_TEMP_REG;//we read 16bits here if we want to change just 8 and leave the rest
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// Execution units
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@ -91,7 +96,7 @@ always @(negedge reset) begin
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@(posedge reset)
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@(negedge clock);
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state=`PROC_IF_STATE_ENTRY;
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IN_MOD=2'b11;
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MOD=2'b11;
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ERROR=0;
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end
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end
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@ -134,7 +139,7 @@ ALU ALU(ALU_1A,ALU_1B,ALU_1OE,ALU_1O,ALU_1OP,ALU_FLAGS,Wbit);
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/*** Processor stages ***/
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`define invalid_instruction state=`PROC_IF_STATE_ENTRY;ERROR=1;IN_MOD=2'b11;
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`define invalid_instruction state=`PROC_IF_STATE_ENTRY;ERROR=1;MOD=2'b11;
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`define start_aligning_instruction if(unaligned_access==0)begin ProgCount=ProgCount+1; external_address_bus <= ProgCount; end /*we normally don't advance PC in case of singly byte unaligning instructions leaving us with two instructions in one read so do that here*/
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`define start_unaligning_instruction unaligned_access=~unaligned_access;
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@ -156,6 +161,50 @@ always @(negedge clock) begin
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end
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`PROC_EX_STATE_EXIT:begin
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case(out_sel)
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3'b000,
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3'b001,
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3'b010 : begin
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case (RM) /* Duplicate code with write... */
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3'b000:begin
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/*[BX]+[SI]*/
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`invalid_instruction
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end
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3'b001:begin
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/*[BX]+[SI]*/
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`invalid_instruction
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end
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3'b010:begin
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/*[BP]+[SI]*/
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`invalid_instruction
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end
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3'b011:begin
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/*[BP]+[DI]*/
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`invalid_instruction
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end
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3'b100:begin
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/*[SI]*/
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reg_read_addr=4'b1110;
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reg_read_oe=0;
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state=`PROC_MEMIO_WRITE;
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end
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3'b101:begin
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/*[DI]*/
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reg_read_addr=4'b1111;
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reg_read_oe=0;
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state=`PROC_MEMIO_WRITE;
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end
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3'b110:begin
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/*d16 */
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`invalid_instruction
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end
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3'b111:begin
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/*[BX]*/
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reg_read_addr=4'b1011;
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reg_read_oe=0;
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state=`PROC_MEMIO_WRITE;
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end
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endcase
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end
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3'b011:begin
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reg_write_we=0;
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state=`PROC_IF_STATE_ENTRY;
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@ -177,10 +226,18 @@ always @(negedge clock) begin
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external_address_bus = ProgCount;
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state=`PROC_DE_LOAD_16_EXTRA_FETCH;
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end
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`PROC_MEMIO_SETADDR:begin
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`PROC_MEMIO_READ_SETADDR:begin
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external_address_bus = {1'b0,reg_read_data[15:1]};
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state=reg_read_data[0:0]?`PROC_MEMIO_GET_UNALIGNED_DATA:`PROC_MEMIO_GET_ALIGNED_DATA;
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end
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`PROC_MEMIO_PUT_BYTE:begin
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BYTE_WRITE_TEMP_REG=external_data_bus;
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state=`PROC_MEMIO_PUT_BYTE_STOP_READ;
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end
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`PROC_MEMIO_PUT_BYTE_WRITE:begin
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write=0;
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state=`PROC_IF_STATE_ENTRY;
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end
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endcase
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end
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@ -225,7 +282,7 @@ always @(posedge clock) begin
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`start_unaligning_instruction
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else
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`start_aligning_instruction
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IN_MOD=2'b11;
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MOD=2'b11;
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in1_sel=2'b00;
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in2_sel=2'b01;
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out_sel=3'b011;
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@ -252,7 +309,7 @@ always @(posedge clock) begin
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/* 1 0 0 0 0 0 S W | MOD 0 0 0 R/M | < DISP LO > | < DISP HI > | DATA | DATA if W | */
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`start_aligning_instruction
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Wbit=CIR[8:8];
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IN_MOD=2'b11;
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MOD=2'b11;
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in1_sel=2'b00;
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in2_sel=2'b01;
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out_sel={1'b0,CIR[7:6]};
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@ -282,7 +339,7 @@ always @(posedge clock) begin
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`start_unaligning_instruction
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else
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`start_aligning_instruction
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IN_MOD=2'b11;
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MOD=2'b11;
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in1_sel=2'b00;
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in2_sel=2'b00;
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out_sel=3'b011;
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@ -301,7 +358,7 @@ always @(posedge clock) begin
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`start_unaligning_instruction
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else
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`start_aligning_instruction
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IN_MOD=2'b11;
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MOD=2'b11;
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in1_sel=2'b00;
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in2_sel=2'b00;
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out_sel=3'b011;
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@ -316,13 +373,13 @@ always @(posedge clock) begin
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/* MOV - Reg/Mem to/from register */
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/* 1 0 0 0 1 0 D W | MOD REG REG | < DISP LO > | < DISP HI > |*/
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`start_aligning_instruction
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IN_MOD=CIR[7:6];
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IN_RM=CIR[2:0];
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MOD=CIR[7:6];
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RM=CIR[2:0];
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Wbit=CIR[8:8];
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if(CIR[9:9] == 1)begin
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/* to reg */
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IN_MOD=CIR[7:6];
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if(IN_MOD==2'b11)begin
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MOD=CIR[7:6];
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if(MOD==2'b11)begin
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in1_sel=2'b01;
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reg_read_addr=CIR[2:0];
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end else begin
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@ -339,7 +396,7 @@ always @(posedge clock) begin
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ALU_1OP=`ALU_OP_ADD;
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PARAM2=0;
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state=`PROC_DE_LOAD_16_PARAM;
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if ( IN_MOD == 2'b11 )
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if ( MOD == 2'b11 )
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state=`PROC_EX_STATE_ENTRY;
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else
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state=`RPOC_MEMIO_READ;
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@ -357,7 +414,7 @@ always @(posedge clock) begin
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in1_sel=2'b01;
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in2_sel=2'b00;
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out_sel=3'b011;
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IN_MOD=2'b11;
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MOD=2'b11;
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PARAM2=1;
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reg_read_addr={1'b1,CIR[10:8]};
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reg_write_addr={1'b1,CIR[10:8]};
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@ -378,14 +435,18 @@ always @(posedge clock) begin
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/* 1 1 1 1 1 1 1 W | MOD 0 0 0 R/M | < DISP LO> | < DISP HI> */
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`start_aligning_instruction
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Wbit=CIR[8:8];
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IN_MOD=CIR[7:6];
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in1_sel=2'b00;/* number 1 */
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in2_sel=(CIR[7:6]==2'b11)? 2'b01 : 2'b00;
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out_sel={1'b0,CIR[7:6]};
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PARAM1=1;
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reg_read_addr={1'b0,CIR[2:0]};
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reg_write_addr={1'b0,CIR[2:0]};
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MOD=CIR[7:6];
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RM=CIR[2:0];
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in1_sel=(MOD==2'b11)? 2'b01 : 2'b00;
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in2_sel=2'b00;/* number 1 */
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out_sel={1'b0,MOD};
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PARAM2=1;
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/*in case MOD=11 */
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reg_read_addr={1'b0,RM};
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reg_write_addr={1'b0,RM};
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reg_read_oe=0;
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ALU_1OE=0;
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ALU_1OP=`ALU_OP_ADD;
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if ( CIR[7:6] == 2'b11 )
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@ -408,7 +469,7 @@ always @(posedge clock) begin
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/* HLT - Halt */
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/* 1 1 1 1 0 1 0 0 | */
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`start_unaligning_instruction
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IN_MOD=2'b11;
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MOD=2'b11;
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HALT=1;
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state=`PROC_HALT_STATE;
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end
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@ -430,7 +491,7 @@ always @(posedge clock) begin
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`start_unaligning_instruction
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else
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`start_aligning_instruction
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IN_MOD=2'b11;
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MOD=2'b11;
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in1_sel=2'b00;
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in2_sel=2'b01;
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reg_read_addr={CIR[8:8],3'b000};
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@ -530,7 +591,7 @@ always @(posedge clock) begin
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end
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`RPOC_MEMIO_READ:begin
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/*Decode MOD R/M, read the data and place it to PARAM1*/
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case (IN_RM)
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case (RM)
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3'b000:begin
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/*[BX]+[SI]*/
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`invalid_instruction
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@ -551,13 +612,13 @@ always @(posedge clock) begin
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/*[SI]*/
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reg_read_addr=4'b1110;
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reg_read_oe=0;
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state=`PROC_MEMIO_SETADDR;
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state=`PROC_MEMIO_READ_SETADDR;
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end
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3'b101:begin
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/*[DI]*/
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reg_read_addr=4'b1111;
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reg_read_oe=0;
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state=`PROC_MEMIO_SETADDR;
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state=`PROC_MEMIO_READ_SETADDR;
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end
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3'b110:begin
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/*d16 */
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@ -567,10 +628,10 @@ always @(posedge clock) begin
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/*[BX]*/
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reg_read_addr=4'b1011;
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reg_read_oe=0;
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state=`PROC_MEMIO_SETADDR;
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state=`PROC_MEMIO_READ_SETADDR;
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end
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endcase
|
||||
if(IN_MOD!=2'b00)begin
|
||||
if(MOD!=2'b00)begin
|
||||
/*Actually check if 01 and add the 8bits or if 10 add the 16bits ....*/
|
||||
`invalid_instruction;
|
||||
end
|
||||
@ -593,6 +654,18 @@ always @(posedge clock) begin
|
||||
FLAGS[7:0] = ALU_FLAGS[7:0];
|
||||
state=`PROC_EX_STATE_EXIT;
|
||||
end
|
||||
`PROC_MEMIO_WRITE:begin
|
||||
external_address_bus = {1'b0,reg_read_data[15:1]};
|
||||
state = (Wbit==0) ? `PROC_MEMIO_PUT_BYTE : (reg_read_data[0:0]?`PROC_MEMIO_PUT_UNALIGNED_DATA:`PROC_MEMIO_PUT_ALIGNED_DATA) ;
|
||||
end
|
||||
`PROC_MEMIO_PUT_BYTE_STOP_READ:begin
|
||||
read=1;
|
||||
state=`PROC_MEMIO_PUT_BYTE_WRITE;
|
||||
if(reg_read_data[0:0]==0)
|
||||
data_bus_output_register={ALU_1O[7:0],BYTE_WRITE_TEMP_REG[7:0]};
|
||||
else
|
||||
data_bus_output_register={BYTE_WRITE_TEMP_REG[15:8],ALU_1O[7:0]};
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
|
||||
@ -29,7 +29,7 @@ wire rd,wr,romcs,HALT;
|
||||
wire ERROR;
|
||||
|
||||
processor p(clock,reset,address_bus,data_bus,rd,wr,HALT,ERROR);
|
||||
rom bootrom(address_bus,data_bus,rd,romcs);
|
||||
mem sysmem(address_bus,data_bus,rd,wr,romcs);
|
||||
|
||||
`define CPU_SPEED 1000
|
||||
|
||||
@ -51,7 +51,7 @@ end
|
||||
|
||||
always @(posedge HALT) begin
|
||||
$display("Processor halted.\nCycles run for: %d",cycles);
|
||||
$writememh("memdump.txt", bootrom.memory);
|
||||
$writememh("memdump.txt", sysmem.memory);
|
||||
#(`CPU_SPEED) //Just for the waveform
|
||||
$finish;
|
||||
end
|
||||
@ -59,7 +59,7 @@ end
|
||||
always @(posedge ERROR) begin
|
||||
clk_enable <= 0;
|
||||
$display("PROCESSOR RUN INTO AN ERROR.\nCycles run for: %d",cycles);
|
||||
$writememh("memdump.txt", bootrom.memory);
|
||||
$writememh("memdump.txt", sysmem.memory);
|
||||
#(`CPU_SPEED) //Just for the waveform
|
||||
$finish;
|
||||
end
|
||||
|
||||
Loading…
Reference in New Issue
Block a user