Efthimis/9086
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases 1 Wiki Activity
A CPU that aims to be binary compatible with the 8086 ISA, focused on optimisation and flexibility.
73 Commits 2 Branches 4 Tags 1.8 MiB
Verilog 66.9%
Makefile 9.9%
Assembly 9.4%
Shell 6.9%
Brainfuck 5.9%
Other 1%
ba52ff89e6
Go to file
(Tim) Efthimis Kritikos ba52ff89e6 Fixed most problems verilator's linter found
2023-03-04 06:22:28 +00:00
boot_code Cleaned up boot_code 2023-03-03 19:36:28 +00:00
readme_files Fixed register addressing bug, mem read endianness, cleaned up code and added a provisional project logo 2023-02-19 00:20:53 +00:00
system Fixed most problems verilator's linter found 2023-03-04 06:22:28 +00:00
.gitignore Cleaned up boot_code 2023-03-03 19:36:28 +00:00
8086_documentation.md Overhauled cpu frontend. Made memory byte addressable (necessary), cleaned up state machine and fixed small bug with MOV 2023-03-03 06:29:06 +00:00
common.mk Increased the accessible memory and got the Mandelbrot renderer working under the brainfuck compiler! 2023-02-24 17:38:23 +00:00
COPYING Properly licensed the project and run it through aspell 2023-02-13 16:49:17 +00:00
gtkwave_savefile.gtkw Added Microcode support, Stack, implemented the CALL instruction in microcode and grouped the wires on the decoder module 2023-02-22 01:28:23 +00:00
Makefile Cleaned up boot_code 2023-03-03 19:36:28 +00:00
README.md Updated toolchain versions and run project through aspell 2023-03-03 06:54:33 +00:00

README.md

9086 logo

A CPU that aims to be binary compatible with the 8086 and with as many optimisations as possible

Progress

  • Executing code
  • Is Turing complete
  • Can boot up MS-DOS / FreeDOS
  • Is completely binary compatible
  • Is pipelined
  • Is Out of Order
  • Is superscalar
  • Has been successfully synthesized

Simulating it

To simulate this project you need Icarus Verilog, bin86, GNU make, xxd and the posix coreutils. After that you can run make on the top level directory and it should build everything and start the simulation

At the time of development the versions used are :

  • Icarus Verilog version 11.0 (stable)
  • bin86 version: 0.16.21
  • GNU Make 4.4.1
  • xxd 2022-01-14
  • GNU coreutils 9.1

License

All parts of this project are licensed under the GNU General Public License version 3 or later