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It is Turing complete! Running the Mandelbrot renderer with the brainfuck interpreter. Improved addressing modes and added CMP immediate with register instruction

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This commit is contained in:
(Tim) Efthimis Kritikos 2023-02-15 03:53:05 +00:00
parent f4d28cf4c8
commit 5e0c990394
9 changed files with 110 additions and 16 deletions
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2
README.md
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@ -4,7 +4,7 @@ A CPU that aims to be binary compatible with the 8086 and with as many optimisat
### Progress
* [X] Executing code
* [ ] Is Turing complete
* [X] Is Turing complete
* [ ] Can boot up MS-DOS / FreeDOS
* [ ] Is completely binary compatible
* [ ] Is pipelined

2
cpu/Makefile
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@ -42,7 +42,7 @@ ${VVP} : ${SOURCES} ${INCLUDES}
iverilog -g2012 ${SOURCES} -o $@
%.txt:%.bin
dd if=/dev/zero bs=1 count=1200 of=$(subst .bin,.stage,$^) status=none
dd if=/dev/zero bs=1 count=16384 of=$(subst .bin,.stage,$^) status=none
dd if=$^ of=$(subst .bin,.stage,$^) conv=notrunc,nocreat status=none
xxd -ps -c 2 $(subst .bin,.stage,$^) > $@
rm $(subst .bin,.stage,$^)

9
cpu/boot_code.asm
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@ -1,3 +1,4 @@
start:
MOV AX,#0x0000
MOV CX,#0x0000
MOV BX,#0x0000
@ -9,6 +10,12 @@ inc AL
mov AX,#0x00FF
inc ax
ADD AX,#0x2200
MOV SI,#0x0102
MOV SI,#0x0101
MOV [SI],AX
inc [si]
inc [si]
inc [si]
dec [si]
cmp CX,#0x00
jz start
HLT

2
cpu/brainfuck.asm
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@ -94,10 +94,8 @@ WAS_PR:
mov AL,[BX]
cmp AL,#0
JZ EXIT_PR
push SI
MOV SI,CX
mov ax,[SI]
POP SI
mov si,ax
JMP INTERPRET

5
cpu/config.v
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@ -18,5 +18,6 @@
along with this program. If not, see <http://www.gnu.org/licenses/>. */
//Runtime Verbosity
`define DEBUG_REG_WRITES
`define DEBUG_PC_ADDRESS
//`define DEBUG_REG_WRITES
//`define DEBUG_PC_ADDRESS
//`define DEBUG_MEMORY_WRITES

2
cpu/memory.v
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@ -18,7 +18,7 @@
along with this program. If not, see <http://www.gnu.org/licenses/>. */
module mem(input [19:0] address,inout wire [15:0] data ,input rd,input wr,input cs);
reg [15:0] memory [0:599];
reg [15:0] memory [0:8191];
initial begin
string boot_code;
if(!$value$plusargs("BOOT_CODE=%s",boot_code))

10
cpu/proc_state_def.v
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@ -34,12 +34,17 @@
`define PROC_DE_LOAD_16_PARAM 5'b01001
`define PROC_DE_LOAD_16_EXTRA_FETCH_SET 5'b01010
`define PROC_DE_LOAD_16_EXTRA_FETCH 5'b01011
`define PROC_DE_LOAD_REG_TO_PARAM 5'b11011 /****/
/*MEM/IO READ*/
`define RPOC_MEMIO_READ 5'b10000
`define PROC_MEMIO_READ_SETADDR 5'b10001
`define PROC_MEMIO_GET_ALIGNED_DATA 5'b10010 /* :) */
`define PROC_MEMIO_GET_UNALIGNED_DATA 5'b10011 /* :( */
`define PROC_MEMIO_GET_SECOND_BYTE 5'b11100 /******/
`define PROC_MEMIO_GET_SECOND_BYTE1 5'b11101 /******/
`define PROC_DE_LOAD_8_PARAM 5'b00110 /******/
`define PROC_DE_LOAD_8_PARAM_UNALIGNED 5'b00111 /******/
/*EXECUTE STATE*/
`define PROC_EX_STATE_ENTRY 5'b11000
@ -57,6 +62,5 @@
`define PROC_MEMIO_PUT_UNALIGNED_PREP_NEXT 5'b01100 /****/
`define PROC_MEMIO_PUT_UNALIGNED_PREP_NEXT1 5'b01101 /****/
`define PROC_MEMIO_PUT_UNALIGNED_PREP_NEXT2 5'b01110 /****/
`define PROC_MEMIO_PUT_UNALIGNED_PREP_NEXT3 5'b01111
`define PROC_MEMIO_PUT_UNALIGNED_PREP_NEXT4 5'b11010
`define PROC_DE_LOAD_REG_TO_PARAM 5'b11011
`define PROC_MEMIO_PUT_UNALIGNED_PREP_NEXT3 5'b01111 /****/
`define PROC_MEMIO_PUT_UNALIGNED_PREP_NEXT4 5'b11010 /****/

94
cpu/processor.v
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@ -51,6 +51,7 @@ reg unaligned_access;
reg [1:0]MOD;
reg [2:0]RM;
reg Wbit;
reg Sbit;
reg [15:0]FLAGS;
/* . . . . O D I T S Z . A . P . C */
// C - Carry flag : carry out or borrow into the high order bit (8bit/16bit)
@ -258,6 +259,18 @@ always @(negedge clock) begin
BYTE_WRITE_TEMP_REG=external_data_bus;
state=`PROC_MEMIO_PUT_UNALIGNED_PREP_NEXT4;
end
`PROC_MEMIO_GET_SECOND_BYTE:begin
external_address_bus=external_address_bus+1;
state=`PROC_MEMIO_GET_SECOND_BYTE1;
end
`PROC_DE_LOAD_8_PARAM_UNALIGNED:begin
if({Sbit,Wbit}==2'b11)begin
PARAM1 = {{8{external_data_bus[15:15]}},external_data_bus[15:8]};
end else begin
PARAM1[7:0] = external_data_bus[15:8];
end
state=`PROC_EX_STATE_ENTRY;
end
endcase
end
@ -343,6 +356,30 @@ always @(posedge clock) begin
`invalid_instruction /*do 8bit loads*/
end
end
3'b111 : begin
/* CMP - compare Immediate with register / memory */
/* 1 0 0 0 0 0 S W | MOD 0 0 0 R/M | < DISP LO > | < DISP HI > | DATA | DATA if W | */
Wbit=CIR[8:8];
Sbit=CIR[9:9];
MOD=CIR[7:6];
if((Wbit==1)&&(CIR[9:9]==1))begin
`start_unaligning_instruction
end else begin
`invalid_instruction;
end
if(MOD==2'b11)begin
in_alu1_sel1=2'b00;
in_alu1_sel2=2'b01;
reg_read_port1_addr={CIR[8:8],CIR[2:0]};
out_alu1_sel=3'b100;
ALU_1OE=0;
ALU_1OP=`ALU_OP_SUB;
state=`PROC_DE_LOAD_8_PARAM;
end else begin
`invalid_instruction
end
end
default:begin
`invalid_instruction
end
@ -459,9 +496,11 @@ always @(posedge clock) begin
/* INC */
if (CIR[9:9] == 1 ) begin
case (CIR[5:3])
3'b000 :begin
3'b000,3'b001 :begin
/* INC - Register/Memory */
/* 1 1 1 1 1 1 1 W | MOD 0 0 0 R/M | < DISP LO> | < DISP HI> */
/* DEC - Register/Memory */
/* 1 1 1 1 1 1 1 W | MOD 0 0 1 R/M | < DISP LO> | < DISP HI> */
`start_aligning_instruction
Wbit=CIR[8:8];
MOD=CIR[7:6];
@ -476,7 +515,7 @@ always @(posedge clock) begin
reg_write_addr={1'b0,RM};
ALU_1OE=0;
ALU_1OP=`ALU_OP_ADD;
ALU_1OP=(CIR[3:3]==1)?`ALU_OP_SUB:`ALU_OP_ADD;
if ( CIR[7:6] == 2'b11 )
state=`PROC_EX_STATE_ENTRY;
else
@ -624,6 +663,31 @@ always @(posedge clock) begin
end
endcase
end
6'b110011:begin
case(CIR[9:8])
2'b00:begin
`invalid_instruction
end
2'b01:begin
if(CIR[7:0]==8'h21) begin
/* INT - execut interrupt handler */
/* 1 1 0 0 1 1 0 1 | DATA |*/
`start_aligning_instruction
/* Emulate MS-DOS print routines */
$write("%s" ,register_file.registers[2][7:0]);
state=`PROC_IF_STATE_ENTRY;
end else begin
`invalid_instruction
end
end
2'b10:begin
`invalid_instruction
end
2'b11:begin
`invalid_instruction
end
endcase
end
default:begin
`invalid_instruction
end
@ -633,6 +697,20 @@ always @(posedge clock) begin
PARAM1=reg_read_port1_data;
state=`PROC_EX_STATE_ENTRY;
end
`PROC_DE_LOAD_8_PARAM:begin
ProgCount=ProgCount+1;
if(unaligned_access==0)begin
if({Sbit,Wbit}==2'b11)begin
PARAM1 = {{8{external_data_bus[7:7]}},external_data_bus[7:0]};
end else begin
PARAM1[7:0] = external_data_bus[7:0];
end
state=`PROC_EX_STATE_ENTRY;
end else begin
external_address_bus=ProgCount;
state=`PROC_DE_LOAD_8_PARAM_UNALIGNED;
end
end
`PROC_DE_LOAD_16_PARAM:begin
if(unaligned_access==1)begin
PARAM1[7:0] = external_data_bus[7:0];
@ -699,10 +777,10 @@ always @(posedge clock) begin
state=`PROC_EX_STATE_ENTRY;
end
`PROC_MEMIO_GET_UNALIGNED_DATA:begin
PARAM1={8'b00000000,external_data_bus[7:0]};
if(Wbit==1) begin
`invalid_instruction //easy to implement, get the other byte from the next address
state=`PROC_MEMIO_GET_SECOND_BYTE;
end else begin
PARAM1={8'b00000000,external_data_bus[7:0]};
state=`PROC_EX_STATE_ENTRY;
end
end
@ -712,7 +790,9 @@ always @(posedge clock) begin
end
`PROC_MEMIO_WRITE:begin
/* ADDRESS: reg_read_port1_data DATA:ALU1_O */
$display("Writing at %04x , %04x",reg_read_port1_data,ALU_1O);
`ifdef DEBUG_MEMORY_WRITES
$display("Writing at %04x , %04x",reg_read_port1_data,ALU_1O);
`endif
external_address_bus = {1'b0,reg_read_port1_data[15:1]};
state = (Wbit==0) ? `PROC_MEMIO_PUT_BYTE : (reg_read_port1_data[0:0]?`PROC_MEMIO_PUT_UNALIGNED_DATA:`PROC_MEMIO_PUT_ALIGNED_DATA) ;
end
@ -740,6 +820,10 @@ always @(posedge clock) begin
state=`PROC_MEMIO_WRITE_EXIT;
data_bus_output_register={ALU_1O[15:8],BYTE_WRITE_TEMP_REG[7:0]};
end
`PROC_MEMIO_GET_SECOND_BYTE1:begin
PARAM1[15:8]=external_data_bus[15:8];
state=`PROC_EX_STATE_ENTRY;
end
endcase
end

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cpu/test Normal file
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