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A CPU that aims to be binary compatible with the 8086 ISA, focused on optimisation and flexibility.
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(Tim) Efthimis Kritikos fde181aa66 Project: Fixed verilator warnings for fpga_sim
2024-02-26 13:12:26 +00:00
boot_code Peripherals/ascii_to_HD44780_driver: Added support for the \e[H and \e[2J escape codes to clear the screen after the i2c_bootloader is done 2024-02-11 04:35:44 +00:00
readme_files Project: updated copyright notices and README and fixed a few spelling mistakes 2024-02-10 15:52:13 +00:00
system Project: Fixed verilator warnings for fpga_sim 2024-02-26 13:12:26 +00:00
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.gitignore Build system: Added the ability to simulate an FPGA SoC and fixed all the warning verilator gave of the code previously used only for synthesis. 2023-12-07 16:39:04 +00:00
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common.mk Peripherals/I2C: Added a CPU I2C driver and wrote a bootloader that uses that to boot from an I2C eeprom 2024-02-09 23:30:58 +00:00
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Makefile Project: updated copyright notices and README and fixed a few spelling mistakes 2024-02-10 15:52:13 +00:00
README.md Project: updated copyright notices and README and fixed a few spelling mistakes 2024-02-10 15:52:13 +00:00

README.md

9086 logo

A CPU that aims to be binary compatible with the 8086 ISA, focused on optimisation and flexibility.

Progress

  • 8086
    • Executing code
    • Is Turing complete
    • Can boot up MS-DOS / FreeDOS
    • Is completely binary compatible
    • Is pipelined
    • Is Out of Order
    • Is superscalar
    • Has been successfully synthesized
    • Has a comprehensive testing framework

Simulating it

Both Verilator and Icarus Verilog can be used for simulation. You can select which one you want with the SIM variable on ./common.mk. This list shows the software needed and the versions used during development :

  • Icarus Verilog : version 12.0 OR (preferred) Verilator : 5.018
  • bin86 : 0.16.21
  • GNU Make : 4.4.1
  • xxd : 2023-10-25
  • POSIX coreutils : GNU coreutils 9.4

After that you can run make on the top level directory and it should build everything and start the simulation

Synthesis and bitstream creation for FPGAs

You need to set FPGA_BOARD in ./common.mk to the name of a directory inside ./system/fpga_config/. You should also check inside your board directory for config.mk for further board-specific configuration options like the model of I2C boot rom (if any). Then you can run make upload_bitstream in the top level directory and it should create the bitstream and upload it to the fpga. Depending on the board you might need to run make upload_bootrom to upload the boot code to an I2C eeprom.

These are the currently supported FPGA boards:

  • OrangeCrab r0.2.1

This list shows the software needed and the versions used during development :

  • yosys : 0.37
  • bin86 : 0.16.21
  • GNU Make : 4.4.1
  • xxd : 2023-10-25
  • POSIX coreutils : GNU coreutils 9.4

Additionally, for ECP5 FPGAs:

  • prjtrellis : 1.4 ( database commit 4dda149b9e4f1753ebc8b011ece2fe794be1281a )
  • nextpnr : 0.6

Additionally, for FPGAs using the foboot bootloader

  • dfu-util : 0.11

Additionally, for boards that require an I2C eeprom to boot from

  • minipro : 0.6 - ( git commit a227bce77d1b592785558e0af58ae2b0b97d4a23 )

Additionally, if you need a DRAM/DDR controller, the project supports litedram but all the dependencies needed to build it are downloaded automatically by the appropriate script.

High level design overview

9086 logo

License and Copyright

All parts of this project and files in this repository are licensed under the GNU General Public License version 3 or later

Efthymios Kritikos is the copyright owner for all files except the following:

File Copyright owner Original license
system/fpga_config/OrangeCrab_r0.2.1/pin_constraint.pcf Greg Davill MIT

Version names

The version name consist of three numbers:

  1. The CPU that this version aims to be compatible with
  2. The specific milestone
  3. Patch level

For example v1.3.2 aims to support 80186 code, is on the fourth milestone and has 2 bug fixes since the milestone was reached. A "-dev" suffix denotes that the code is in the process to become that version, so in-between that and the previous.