Implemented PUSH instruction, fixed register addressing bug and a RET bug
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@ -273,7 +273,7 @@ always @( CIR or SIMPLE_MICRO or seq_addr_input ) begin
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/* DEC - Register/Memory */
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/* 1 1 1 1 1 1 1 W | MOD 0 0 1 R/M | < DISP LO> | < DISP HI> */
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seq_addr_entry=`UCODE_NO_INSTRUCTION;
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has_operands=1;
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has_operands=0;
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opcode_size=1;
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`start_aligning_instruction
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Wbit=CIR[8:8];
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@ -414,7 +414,7 @@ always @( CIR or SIMPLE_MICRO or seq_addr_input ) begin
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end
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next_state=`PROC_IF_STATE_ENTRY;
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end
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11'b11101000_xxx:begin
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11'b1110_1000_xxx:begin
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/* CALL - Direct call within segment */
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/* 1 1 1 0 1 0 0 0 | IP-INC-LO | IP-INC-HI |*/
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@ -427,7 +427,7 @@ always @( CIR or SIMPLE_MICRO or seq_addr_input ) begin
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PARAM2=2; //substract from sp
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seq_addr_entry=`UCODE_CALL_ENTRY;
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end
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11'b11000011_xxx:begin
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11'b1100_0011_xxx:begin
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/* RET - Return from call within segment */
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/* | 1 1 0 0 0 0 1 1 | */
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@ -442,10 +442,10 @@ always @( CIR or SIMPLE_MICRO or seq_addr_input ) begin
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has_operands=1;
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Wbit=1;
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Sbit=0;
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PARAM2=2;
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PARAM1=2;
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seq_addr_entry=`UCODE_RET_ENTRY;
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end
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11'b1010101x_xxx:begin
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11'b1010_101x_xxx:begin
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/* STOS - Write byte/word to [DI] and increment accordingly */
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/* | 1 0 1 0 1 0 1 W | */
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`start_unaligning_instruction
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@ -457,6 +457,18 @@ always @( CIR or SIMPLE_MICRO or seq_addr_input ) begin
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seq_addr_entry=`UCODE_STOS_ENTRY;
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PARAM2=(Wbit==1)?2:1;
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end
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11'b0101_0xxx_xxx:begin
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/* PUSH - SP-=2; [SP]=REG */
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/* | 0 1 0 1 0 REG | */
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`start_unaligning_instruction
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opcode_size=0;
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has_operands=0;
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Wbit=1;
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Sbit=0;
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PARAM2=2;
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reg_read_port2_addr={1'b1,CIR[10:8]};
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seq_addr_entry=`UCODE_PUSH_ENTRY;
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end
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default:begin
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`invalid_instruction
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end
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@ -487,9 +499,13 @@ always @( CIR or SIMPLE_MICRO or seq_addr_input ) begin
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3'b101: ALU_1OP=`ALU_OP_ADD_SIGNED_B;
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3'b110: ALU_1OP=`ALU_OP_SUB_REVERSE;
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endcase
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reg_read_port1_addr=ucode_data[25:22];
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IN_MOD =ucode_data[28:26];
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reg_read_port2_addr=ucode_data[32:29];
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if(ucode_data[33:33]==0)
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reg_read_port1_addr=ucode_data[25:22];
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IN_MOD=ucode_data[28:26];
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if(ucode_data[34:34]==0)
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reg_read_port2_addr=ucode_data[32:29];
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if(ucode_data[36:36]==1)
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Wbit=ucode_data[35:35];
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end
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end
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@ -185,7 +185,7 @@ always @(negedge clock) begin
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* be done by decode at the end*/
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if (ucode_seq_addr==`UCODE_NO_INSTRUCTION)
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unaligned_access=unaligning_instruction^unaligned_access;
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case(OUT_MOD) /*TODO: use RM*/
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case(OUT_MOD)
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3'b000,
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3'b001,
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3'b010 : begin
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@ -507,7 +507,7 @@ always @(posedge clock) begin
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end
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end
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`PROC_EX_STATE_ENTRY:begin
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FLAGS[7:0] = ALU_1FLAGS[7:0];
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FLAGS[7:0] = ALU_1FLAGS[7:0]; //TODO, we should probably move all the ...STATE_EXIT stuff here
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state=`PROC_EX_STATE_EXIT;
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end
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`PROC_MEMIO_WRITE:begin
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@ -32,11 +32,13 @@ input write_port1_we;
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reg [15:0] registers [7:0];
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assign read_port1_data = ( read_port1_addr[3:3] ? registers[read_port1_addr[2:0]] :
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( read_port1_addr[2:2] ? {8'b0,registers[read_port1_addr[2:0]][15:8]} : {8'b0,registers[read_port1_addr[2:0]][7:0]} ) );
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assign read_port1_data[15:8] = read_port1_addr[3:3] ? registers[read_port1_addr[2:0]][15:8] : 8'hz ;
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assign read_port1_data[7:0] = ( read_port1_addr[3:3] ? registers[read_port1_addr[2:0]][7:0] :
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( read_port1_addr[2:2] ? {8'b0,registers[read_port1_addr[1:0]][15:8]} : {8'b0,registers[read_port1_addr[1:0]][7:0]} ) );
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assign read_port2_data = ( read_port2_addr[3:3] ? registers[read_port2_addr[2:0]] :
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( read_port2_addr[2:2] ? {8'b0,registers[read_port2_addr[2:0]][15:8]} : {8'b0,registers[read_port2_addr[2:0]][7:0]} ) );
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assign read_port2_data[15:8] = read_port2_addr[3:3] ? registers[read_port2_addr[2:0]][15:8] : 8'hz ;
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assign read_port2_data[7:0] = ( read_port2_addr[3:3] ? registers[read_port2_addr[2:0]][7:0] :
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( read_port2_addr[2:2] ? {8'b0,registers[read_port2_addr[1:0]][15:8]} : {8'b0,registers[read_port2_addr[1:0]][7:0]} ) );
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`ifdef DEBUG_REG_WRITES
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string debug_name;
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@ -17,6 +17,13 @@
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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//wbo: Wbit overwrite, {VALUE,ENABLE}. ex 11 would force one, 10 wouldn't do anything
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//
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//krs: Keep registers, selects weather the register port 1 and/or 2
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// addresses is set on that microcoded instruction or kept as it
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// was before allowing for registers to be parameterised.
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// {Register_port2, Register_port1}
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//
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//rr2: reg_read_port2_addr
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//
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//imd: IN_MOD
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@ -50,19 +57,24 @@
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@000 0000_000_000__00__00_0000__00_000000
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// 32 28 25 21 18 15 13 11 7 5 0
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// 36 34 32 28 25 21 18 15 13 11 7 5 0
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// CALL
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// rr2 |imd|rr1 |a1f|a1o|a12|a11|rwa |nxs|Nxt M |
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@001 0000_011_1100_001_011__00__01_1100__01_000010 // ALU_1: SP ALU_2: PARAM2 (2) ALU_OP:SUB ALU_out: SP (also fetch the opcode argument to PARAM1)
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@002 0000_011_zzzz_000_110__10__11_zzzz__00_000011 // ALU_1: 0 ALU_2: PC ALU_OP:ADD ALU_out: [SP]
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@003 0000_011_zzzz_000_101__10__00_zzzz__00_000000 // ALU_1: PARAM1 (arg) ALU_2: PC ALU_OP:ADD ALU_out: PC
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// wbo|krs|rr2 |imd|rr1 |a1f|a1o|a12|a11|rwa |nxs|Nxt M |
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@001 _00_00_0000_011_1100_001_011__00__01_1100__01_000010 // ALU_1: SP ALU_2: PARAM2 (2) ALU_OP:SUB ALU_out: SP (also fetch the opcode argument to PARAM1)
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@002 _00_00_0000_011_zzzz_000_110__10__11_zzzz__00_000011 // ALU_1: 0 ALU_2: PC ALU_OP:ADD ALU_out: [SP]
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@003 _00_00_0000_011_zzzz_000_101__10__00_zzzz__00_000000 // ALU_1: PARAM1 (arg) ALU_2: PC ALU_OP:ADD ALU_out: PC
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// RET
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// rr2 |imd|rr1 |a1f|a1o|a12|a11|rwa |nxs|Nxt M |
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@004 0000_110_zzzz_000_101__00__11_zzzz__11_000101 // ALU_1: 0 ALU_2: PARAM2 ([SP) ALU_OP:ADD ALU_out: PC (also read [SP] to PARAM2)
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@005 0000_011_1100_000_011__01__00_1100__00_000000 // ALU_1: PARAM1 (2) ALU_2: SP ALU_OP:ADD ALU_out: SP
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// wbo|krs|rr2 |imd|rr1 |a1f|a1o|a12|a11|rwa |nxs|Nxt M |
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@004 _00_00_0000_110_zzzz_000_101__00__11_zzzz__11_000101 // ALU_1: 0 ALU_2: PARAM2 ([SP]) ALU_OP:ADD ALU_out: PC (also read [SP] to PARAM2)
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@005 _00_00_1100_011_0000_000_011__01__00_1100__00_000000 // ALU_1: PARAM1 (2) ALU_2: SP ALU_OP:ADD ALU_out: SP
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// STOS
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// rr2 |imd|rr1 |a1f|a1o|a12|a11|rwa |nxs|Nxt M |
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@006 1000_011_zzzz_000_000__01__11_zzzz__00_000111 // ALU_1: 0 ALU_2: AX ALU_OP:ADD ALU_out: [DI]
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@007 zzzz_011_1111_000_011__00__01_1111__00_000000 // ALU_1: DI ALU_2: PARAM2 (2) ALU_OP:ADD ALU_OUT: DI
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// wbo|krs|rr2 |imd|rr1 |a1f|a1o|a12|a11|rwa |nxs|Nxt M |
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@006 _00_00_1000_011_zzzz_000_000__01__11_zzzz__00_000111 // ALU_1: 0 ALU_2: AX ALU_OP:ADD ALU_out: [DI]
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@007 _11_00_zzzz_011_1111_000_011__00__01_1111__00_000000 // ALU_1: DI ALU_2: PARAM2 (2) ALU_OP:ADD ALU_OUT: DI
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// PUSH
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// wbo|krs|rr2 |imd|rr1 |a1f|a1o|a12|a11|rwa |nxs|Nxt M |
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@008 _00_10_0000_011_1100_001_011__00__01_1100__00_001001 // ALU_1: SP ALU_2: PARAM2 (2) ALU_OP:SUB ALU_out: SP (also fetch the opcode argument to PARAM1)
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@009 _00_10_0000_011_zzzz_000_110__01__11_zzzz__00_000000 // ALU_1: 0 ALU_2: REG ALU_OP:ADD ALU_out: [SP]
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@ -18,11 +18,12 @@
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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`define UCODE_ADDR_BITS 5
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`define UCODE_DATA_BITS 33
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`define UCODE_SIZE 8
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`define UCODE_DATA_BITS 37
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`define UCODE_SIZE 10
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/* DEFINE ADDRESSES IN THE MICROCODE */
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`define UCODE_NO_INSTRUCTION 5'b00000
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`define UCODE_CALL_ENTRY 5'b00001
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`define UCODE_RET_ENTRY 5'b00100
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`define UCODE_STOS_ENTRY 5'b00110
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`define UCODE_PUSH_ENTRY 5'b01000
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