Efthimis/9086
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A CPU that aims to be binary compatible with the 8086 ISA, focused on optimisation and flexibility.
46 Commits 2 Branches 4 Tags 1.8 MiB
Verilog 66.9%
Makefile 9.9%
Assembly 9.4%
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(Tim) Efthimis Kritikos fd4a9b5442 Fixed register addressing bug, mem read endianness, cleaned up code and added a provisional project logo
2023-02-19 00:20:53 +00:00
boot_code Fixed register addressing bug, mem read endianness, cleaned up code and added a provisional project logo 2023-02-19 00:20:53 +00:00
readme_files Fixed register addressing bug, mem read endianness, cleaned up code and added a provisional project logo 2023-02-19 00:20:53 +00:00
system Fixed register addressing bug, mem read endianness, cleaned up code and added a provisional project logo 2023-02-19 00:20:53 +00:00
.gitignore Improved build system and project directory structure 2023-02-16 01:52:02 +00:00
8086_documentation.md Fixed register addressing bug, mem read endianness, cleaned up code and added a provisional project logo 2023-02-19 00:20:53 +00:00
common.mk Moved the decoding of opcodes into a separate module and optimised memory reads 2023-02-17 18:08:09 +00:00
COPYING Properly licensed the project and run it through aspell 2023-02-13 16:49:17 +00:00
gtkwave_savefile.gtkw Improved build system and project directory structure 2023-02-16 01:52:02 +00:00
Makefile Further improved build system and changed brainfuck print message 2023-02-16 23:26:32 +00:00
README.md Fixed register addressing bug, mem read endianness, cleaned up code and added a provisional project logo 2023-02-19 00:20:53 +00:00

README.md

9086 logo

A CPU that aims to be binary compatible with the 8086 and with as many optimisations as possible

Progress

  • Executing code
  • Is Turing complete
  • Can boot up MS-DOS / FreeDOS
  • Is completely binary compatible
  • Is pipelined
  • Is Out of Order
  • Is superscalar

Building it

To build this project you need Icarus Verilog, bin86, GNU make, xxd and the posix coreutils and run make on the top level directory.

At the time of development the versions used are :

  • Icarus Verilog version 11.0 (stable)
  • bin86 version: 0.16.17
  • GNU Make 4.3
  • xxd 2022-01-14
  • GNU coreutils 8.32

License

All parts of this project are licensed under the GNU General Public License version 3 or later