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8c921380bc
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Peripherals/BuiltinRam: Fixed high impedance warning in yosys
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2023-12-04 17:04:22 +00:00 |
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374b1946e9
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Added .keep file for intentionally empty directory
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2023-12-03 19:30:59 +00:00 |
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63ea29e399
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Peripherals/Memory: Added support for the litedram DDR memory controller, created a new memory map and updated all relevant code and files including the addition of rudimentary wait state support for the cpu (BIU)
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2023-12-03 19:24:39 +00:00 |
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f1dc9d8a59
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Processor/Instructions: Fixed a bug where if IN executed after a microcoded instruction the cpu would go into undefined behavior
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2023-11-26 00:18:15 +00:00 |
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f07e0e7c1f
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Processor/Instructions: Added support for the IN <immediate> instruction. Also changed some stuff in system.v to add more devices in the IO/Memory space
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2023-11-25 04:12:05 +00:00 |
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17638d5cbd
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Build system: Slight improvements, randomised nextpnr rng seed and printed it to the terminal. In case timing fails running it a bunch of times can yield one value that passes.
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2023-11-23 23:27:19 +00:00 |
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aedefddb5d
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Project: The cpu finally works perfectly now even at full speed as far as i can tell! I made the ram and register writes synchronous which fixed the weird issues I had, then I added -abc9 to yosys so that nextpnr can actually route the cpu at full speed and increased the display fifo since the cpu is so fast now!!
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2023-11-15 18:43:56 +00:00 |
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29bc2e6d96
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Project: Cleaned up some code and run the project through aspell
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2023-11-15 14:37:46 +00:00 |
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98d30a1813
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Project: removed a .fst.hier file thought to be generated by gtkwave and added the type to gitignore
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2023-11-15 00:32:40 +00:00 |
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09ccce5f30
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Peripherals/HD44780: Rewrote and cleaned up a lot of the driver code. Unfortunately what i think is a very weird bug in yosys is still affecting the codebase
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2023-11-15 00:26:46 +00:00 |
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0ca1da81b1
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Assembly code: Fixed a bug where the compiler would print a null byte which was masked by the verilog simulators
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2023-11-14 21:14:45 +00:00 |
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2c8e8a9d9c
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Added simple support for \n and \r on the HD44780 driver, increased the synthesised mem to fit brainfuck_compiled.asm and made it the default.
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2023-11-12 21:39:27 +00:00 |
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189b037bdf
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Added proper line wrapping for HD44780 LCDs and rewrote half the driver to make it more flexible
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2023-11-12 17:30:52 +00:00 |
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618c3102d8
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Fixed some dependencies on the makefiles
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2023-11-12 13:30:12 +00:00 |
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7d2cb5672f
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Reduced numbers to be sorted in gnome_sort.asm to fit in lcd, fixed hlt on real hardware, slowed down cpu, increased lcd fifo and with that I almost got gnome_sort.asm working perfectly on real hardware
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2023-11-12 07:31:05 +00:00 |
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e06c0eeaa0
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Made the build system simplify the microcode so that yosys understands and synthesises it! Now gnome_sort.asm almost works!
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2023-11-12 04:04:56 +00:00 |
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fa62b07c14
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Removed probably unnecessary high impedance case yosys was complaining about in registers.v
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2023-11-12 03:13:22 +00:00 |
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f471b305d8
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Switched some assignments in decode.v to non-blocking which fixed a seemingly unrelated bug with incrementing the accumulator, added some more working test code in colored_led.asm and did some semantic changes as per yosys suggestions
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2023-11-12 02:54:41 +00:00 |
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4c130a8d63
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Added back removed warnings to verilator since we have now fixed those issues
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2023-11-12 00:07:33 +00:00 |
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09b3d51015
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Added statistics to place&route
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2023-11-09 23:10:06 +00:00 |
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863af26422
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Forgot to add the changes to colored_led.asm from the previous commit
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2023-11-09 23:08:12 +00:00 |
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a88c420ca5
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Added an I2C driver, a PCF8574 driver and an HD44780 display driver. Unfortunately this shows that even fibonacci doesn't run correctly. Nonetheless, I made colored_led.asm output text to the display!
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2023-11-09 22:10:55 +00:00 |
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e0dc7bae07
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Move the diagram below some text since it looks a bit ugly this way
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2023-11-07 14:40:51 +00:00 |
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1a1634c673
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Updated README, improved fpga-specific makefile options and updated the version number
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2023-11-07 14:37:22 +00:00 |
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4767a7addc
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Updated progress on README
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2023-11-06 08:18:19 +00:00 |
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01dcbfa7a1
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The CPU works on real hardware for the first time! I added an adjustment for ram size, added control for a led and a test program for it. On the fpga board there is an actual led there that I used to verify functionality
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2023-11-06 08:13:36 +00:00 |
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30ffa1b00c
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Fixed a "combinatorial loop" and now if the build-in memory is reduced the design can be synthesized!
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2023-11-06 05:36:04 +00:00 |
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5ebd53b11c
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fixed more driver conflicts
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2023-11-06 01:35:48 +00:00 |
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ae16c79b0a
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Fixed another driver conflict
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2023-11-05 20:18:11 +00:00 |
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9947517693
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Fixed simulation with icarus verilog and removed another driver conflict
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2023-11-05 19:43:49 +00:00 |
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4a5df9c74e
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Fixed another driver conflict
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2023-11-05 16:23:05 +00:00 |
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aa9b7c0a50
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Removed more "conflicting driver" issues with yet more performance penalties...
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2023-11-04 15:33:23 +00:00 |
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df2975fa09
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Fixed a lot of "conflicting driver" issues but I had to roll back an optimisation
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2023-11-04 11:04:22 +00:00 |
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c7ddf3fa9e
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More small fixes
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2023-11-04 08:31:05 +00:00 |
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694f708a32
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Fixed some relatively low hanging fruit
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2023-11-04 08:08:22 +00:00 |
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934e2f5a36
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Fixed a bunch of things wrong with fpga_top.v and gated off some more simulation-only code
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2023-11-02 23:46:12 +00:00 |
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08aac5c7b6
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Removed some code that wasn't meant for synthesis and fixed important bug in Makefile
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2023-11-02 22:19:15 +00:00 |
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601397b7f0
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Properly added fpga_top.v stuff in the build system and fixed some syntax errors
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2023-11-02 22:00:07 +00:00 |
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43f3e16ca4
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Removed all instances of inout since from what i understand it's mostly synthesisable
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2023-11-02 21:48:12 +00:00 |
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36bf8f9c7a
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Added OrangeCrab board-specific code to connect the cpu to the outside world
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2023-11-02 20:40:04 +00:00 |
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5feee9de57
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Added support to the build system for synthesising, place and routing, serialising and uploading the design to a Lattice ECP5 OrangeCrab FPGA
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2023-11-02 00:29:14 +00:00 |
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85512d5ace
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Last minute fix of dependencies in Makefile before release
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2023-11-01 19:09:59 +00:00 |
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b2972c9938
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release v0.2.0 - Pipelined milestone
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2023-11-01 06:08:12 +00:00 |
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3ec90b1843
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Added version stamp and last commit to json log
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2023-11-01 06:03:53 +00:00 |
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557d160be6
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did some cleanup relating to the generation of the VALID_INSTRUCTION signal
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2023-11-01 05:00:09 +00:00 |
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3a63e916f5
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Added cycles to waveform capture for icarus verilog
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2023-10-31 19:32:35 +00:00 |
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49335a2c2f
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Fixed a small bug in log generation and did some cleanup
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2023-10-31 19:01:34 +00:00 |
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8a62b89a13
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Fixed small bug with json data reporting and improved slightly the graphs
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2023-10-30 08:01:03 +00:00 |
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cfed0b4117
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Made the temporary logo a bit more centered. Also removed an incorrect line in README
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2023-10-24 01:08:13 +01:00 |
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4c28f98797
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Updated the high level design overview diagram
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2023-10-23 13:28:58 +01:00 |
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