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A CPU that aims to be binary compatible with the 8086 ISA, focused on optimisation and flexibility.
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(Tim) Efthimis Kritikos 189b037bdf Added proper line wrapping for HD44780 LCDs and rewrote half the driver to make it more flexible
2023-11-12 17:30:52 +00:00
boot_code Fixed some dependencies on the makefiles 2023-11-12 13:30:12 +00:00
readme_files Made the temporary logo a bit more centered. Also removed an incorrect line in README 2023-10-24 01:08:13 +01:00
system Added proper line wrapping for HD44780 LCDs and rewrote half the driver to make it more flexible 2023-11-12 17:30:52 +00:00
tools Added statistics to place&route 2023-11-09 23:10:06 +00:00
.gitignore Made the build system simplify the microcode so that yosys understands and synthesises it! Now gnome_sort.asm almost works! 2023-11-12 04:04:56 +00:00
8086_documentation.md Changed slogan and cleaned up some small pieces of code 2023-05-23 16:18:33 +01:00
common.mk Updated README, improved fpga-specific makefile options and updated the version number 2023-11-07 14:37:22 +00:00
COPYING Properly licensed the project and run it through aspell 2023-02-13 16:49:17 +00:00
gtkwave_savefile.gtkw Lots of cleanup mainly on processor.v 2023-06-01 02:13:55 +01:00
Makefile Fixed some dependencies on the makefiles 2023-11-12 13:30:12 +00:00
README.md Move the diagram below some text since it looks a bit ugly this way 2023-11-07 14:40:51 +00:00

README.md

9086 logo

A CPU that aims to be binary compatible with the 8086 ISA, focused on optimisation and flexibility.

Progress

  • 8086
    • Executing code
    • Is Turing complete
    • Can boot up MS-DOS / FreeDOS
    • Is completely binary compatible
    • Is pipelined
    • Is Out of Order
    • Is superscalar
    • Has been successfully synthesized
    • Has a comprehensive testing framework

Simulating it

Both Verilator and Icarus Verilog can be used for simulation. You can select which one you want with the SIM variable on ./common.mk. This list shows the software needed and the versions used during development :

  • Icarus Verilog : version 12.0 OR (preferred) Verilator : 5.016
  • bin86 : 0.16.21
  • GNU Make : 4.4.1
  • xxd : 2022-01-14
  • POSIX coreutils : GNU coreutils 9.4

After that you can run make on the top level directory and it should build everything and start the simulation

Synthesis and bitstream creation ( for FPGAs )

Synthesis is based on Yosys. You need to set FPGA_BOARD in ./common.mk to the name of a directory inside ./system/fpga_config/. You should also check inside your board directory for config.mk for further board-specific configuration options. Then you can run make upload in the top level directory and it should create the bitstream and upload it.

These are the currently supported fpga boards:

  • OrangeCrab r0.2.1

This list shows the software needed and the versions used during development :

  • yosys : 0.35
  • bin86 : 0.16.21
  • GNU Make : 4.4.1
  • xxd : 2022-01-14
  • POSIX coreutils : GNU coreutils 9.4

Additionally, for ECP5 FPGAs:

  • prjtrellis : 1.4 ( database commit 4dda149b9e4f1753ebc8b011ece2fe794be1281a )
  • nextpnr : 0.6

Additionally, for FPGAs using the foboot bootloader

  • dfu-util : 0.11

High level design overview

9086 logo

License and Copyright

All parts of this project and files in this repository are licensed under the GNU General Public License version 3 or later

Efthymios Kritikos is the copyright owner for all files except the following:

File Copyright owner Original license
system/fpga_config/OrangeCrab_r0.2.1/pin_constraint.pcf Greg Davill MIT

Version names

The version name consist of three numbers:

  1. The CPU that this version aims to be compatible with
  2. The specific milestone
  3. Patch level

For example v1.3.2 aims to support 80186 code, is on the fourth milestone and has 2 bug fixes since the milestone was reached. A "-dev" suffix denotes that the code is in the process to become that version, so in-between that and the previous.