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A CPU that aims to be binary compatible with the 8086 ISA, focused on optimisation and flexibility.
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(Tim) Efthimis Kritikos 5feee9de57 Added support to the build system for synthesising, place and routing, serialising and uploading the design to a Lattice ECP5 OrangeCrab FPGA
2023-11-02 00:29:14 +00:00
boot_code Added cycles to waveform capture for icarus verilog 2023-10-31 19:32:35 +00:00
readme_files Made the temporary logo a bit more centered. Also removed an incorrect line in README 2023-10-24 01:08:13 +01:00
system Added support to the build system for synthesising, place and routing, serialising and uploading the design to a Lattice ECP5 OrangeCrab FPGA 2023-11-02 00:29:14 +00:00
tools Fixed small bug with json data reporting and improved slightly the graphs 2023-10-30 08:01:03 +00:00
.gitignore Added support to the build system for synthesising, place and routing, serialising and uploading the design to a Lattice ECP5 OrangeCrab FPGA 2023-11-02 00:29:14 +00:00
8086_documentation.md Changed slogan and cleaned up some small pieces of code 2023-05-23 16:18:33 +01:00
common.mk Added support to the build system for synthesising, place and routing, serialising and uploading the design to a Lattice ECP5 OrangeCrab FPGA 2023-11-02 00:29:14 +00:00
COPYING Properly licensed the project and run it through aspell 2023-02-13 16:49:17 +00:00
gtkwave_savefile.gtkw Lots of cleanup mainly on processor.v 2023-06-01 02:13:55 +01:00
Makefile Added support to the build system for synthesising, place and routing, serialising and uploading the design to a Lattice ECP5 OrangeCrab FPGA 2023-11-02 00:29:14 +00:00
README.md Added support to the build system for synthesising, place and routing, serialising and uploading the design to a Lattice ECP5 OrangeCrab FPGA 2023-11-02 00:29:14 +00:00

README.md

9086 logo

A CPU that aims to be binary compatible with the 8086 ISA, focused on optimisation and flexibility.

Progress

  • 8086
    • Executing code
    • Is Turing complete
    • Can boot up MS-DOS / FreeDOS
    • Is completely binary compatible
    • Is pipelined
    • Is Out of Order
    • Is superscalar
    • Has been successfully synthesized

Simulating it

Both Verilator and Icarus Verilog can be used for simulation. You can select which one you want with the SIM variable on common.mk Specifically this list shows the software needed and the versions used during development (other versions should work as well)

  • Icarus Verilog : version 12.0 OR (preferred) Verilator : 5.016
  • bin86 : 0.16.21
  • GNU Make : 4.4.1
  • xxd : 2022-01-14
  • POSIX coreutils : GNU coreutils 9.4

After that you can run make on the top level directory and it should build everything and start the simulation

High level design overview

9086 logo

License

All parts of this project and files in this repository are licensed under the GNU General Public License version 3 or later

Efthymios Kritikos is the copyright owner for all files except the following:

File Copyright owner Original license
system/fpga_config/OrangeCrab_r0.2.1/pin_constraint.pcf Greg Davill MIT

Version names

The version name consist of three numbers:

  1. The CPU that this version aims to be compatible with
  2. The specific milestone
  3. Patch level

For example v1.3.2 aims to support 80186 code, is on the fourth milestone and has 2 bug fixes since the milestone was reached.