Project: The cpu finally works perfectly now even at full speed as far as i can tell! I made the ram and register writes synchronous which fixed the weird issues I had, then I added -abc9 to yosys so that nextpnr can actually route the cpu at full speed and increased the display fifo since the cpu is so fast now!!
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aedefddb5d
@ -77,7 +77,7 @@ simplified_ucode.txt:ucode.txt
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#TODO: we are relying on yosys to trim the input program txt file and hope its enough for the whole program...
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synth_ecp5.json: ${SOURCES} ${TOP_LEVEL_SOURCE} fpga_config/${FPGA_BOARD}/fpga_top.v ${EXTRA_SYNTHESIS_SOURCES} ${INCLUDES} ../boot_code/brainfuck_compiled.txt simplified_ucode.txt
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${QUIET_YOSYS}
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${Q} yosys -q -D BUILTIN_RAM=2048 -D NOT_FULL -p 'read -sv '"${SOURCES} ${TOP_LEVEL_SOURCE} fpga_config/${FPGA_BOARD}/fpga_top.v ${EXTRA_SYNTHESIS_SOURCES} ; synth_ecp5 -json $@ -top fpga_top"
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${Q} yosys -q -D BUILTIN_RAM=2048 -D NOT_FULL -p 'read -sv '"${SOURCES} ${TOP_LEVEL_SOURCE} fpga_config/${FPGA_BOARD}/fpga_top.v ${EXTRA_SYNTHESIS_SOURCES} ; synth_ecp5 -json $@ -abc9 -top fpga_top"
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synth_ecp5_out.config:synth_ecp5.json
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${QUIET_NEXTPNR}
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@ -39,7 +39,7 @@ wire [19:0] address_bus;
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wire [15:0] data_bus_read,data_bus_write;
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wire rd,wr,BHE,IOMEM;
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wire CPU_SPEED=counter[6];
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wire CPU_SPEED=clk48;
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system system(
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/* MISC */ CPU_SPEED,reset
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@ -95,99 +95,21 @@ always @(posedge counter[15]) begin
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endcase
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end
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/* TODO This seems to be a bug with YOSYS. If I don't initialise the memory
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* it doesn't work (even though it does in sim), and for example if i
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* initialise 1 twice to the same value it breaks again.
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*
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* This seems to affect brainfuck_compiled.asm and specifically when the
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* compiled code starts running ( or the compiler i guess )
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*/
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initial begin
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disp_write_cache[ 0]=8'h46;
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disp_write_cache[ 1]=8'h46;
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disp_write_cache[ 2]=8'h46;
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disp_write_cache[ 3]=8'h46;
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disp_write_cache[ 4]=8'h46;
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disp_write_cache[ 5]=8'h46;
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disp_write_cache[ 6]=8'h46;
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disp_write_cache[ 7]=8'h46;
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disp_write_cache[ 8]=8'h46;
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disp_write_cache[ 9]=8'h46;
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disp_write_cache[10]=8'h46;
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disp_write_cache[11]=8'h46;
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disp_write_cache[12]=8'h46;
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disp_write_cache[13]=8'h46;
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disp_write_cache[14]=8'h46;
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disp_write_cache[15]=8'h46;
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disp_write_cache[16]=8'h46;
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disp_write_cache[17]=8'h46;
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disp_write_cache[18]=8'h46;
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disp_write_cache[19]=8'h46;
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disp_write_cache[20]=8'h46;
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disp_write_cache[21]=8'h46;
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disp_write_cache[22]=8'h46;
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disp_write_cache[23]=8'h46;
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disp_write_cache[24]=8'h46;
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disp_write_cache[25]=8'h46;
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disp_write_cache[26]=8'h46;
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disp_write_cache[27]=8'h46;
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disp_write_cache[28]=8'h46;
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disp_write_cache[29]=8'h46;
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disp_write_cache[30]=8'h46;
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disp_write_cache[31]=8'h46;
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disp_write_cache[32]=8'h46;
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disp_write_cache[33]=8'h46;
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disp_write_cache[34]=8'h46;
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disp_write_cache[35]=8'h46;
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disp_write_cache[36]=8'h46;
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disp_write_cache[37]=8'h46;
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disp_write_cache[38]=8'h46;
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disp_write_cache[39]=8'h46;
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disp_write_cache[40]=8'h46;
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disp_write_cache[41]=8'h46;
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disp_write_cache[42]=8'h46;
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disp_write_cache[43]=8'h46;
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disp_write_cache[44]=8'h46;
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disp_write_cache[45]=8'h46;
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disp_write_cache[46]=8'h46;
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disp_write_cache[47]=8'h46;
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disp_write_cache[48]=8'h46;
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disp_write_cache[49]=8'h46;
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disp_write_cache[50]=8'h46;
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disp_write_cache[51]=8'h46;
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disp_write_cache[52]=8'h46;
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disp_write_cache[53]=8'h46;
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disp_write_cache[54]=8'h46;
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disp_write_cache[55]=8'h46;
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disp_write_cache[56]=8'h46;
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disp_write_cache[57]=8'h46;
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disp_write_cache[58]=8'h46;
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disp_write_cache[59]=8'h46;
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disp_write_cache[60]=8'h46;
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disp_write_cache[61]=8'h46;
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disp_write_cache[62]=8'h46;
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disp_write_cache[63]=8'h46;
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end
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//TODO similarly as above, if I remove this the same thing breaks
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always @(negedge wr) begin
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end
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//------------------------------------------//
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// Cache to allow the slow display to have a
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// chance to keep up with the relentless CPU
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reg [5:0] disp_cache_start=0;
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reg [5:0] disp_cache_end=0;
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reg [7:0] disp_write_cache [63:0];
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reg [6:0] disp_cache_start=0;
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reg [6:0] disp_cache_end=0;
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reg [7:0] disp_write_cache [127:0];
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reg ascii_state=0;
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always @(posedge CPU_SPEED)begin
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if(wr==0)begin
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if(IOMEM==1'b1 && address_bus[7:0]==8'hA5 )begin
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disp_write_cache[disp_cache_end]<=data_bus_write[15:8];
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disp_cache_end<=disp_cache_end+6'd1;
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disp_cache_end<=disp_cache_end+7'd1;
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end else if(IOMEM==1'b1 && address_bus[7:0]==8'hB0 )begin
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if(data_bus_write[0:0]==1)
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rgb_led_color=3'b000;
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@ -197,7 +119,7 @@ always @(posedge CPU_SPEED)begin
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end else if(ascii_state==1'b0)begin
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if(ascii_data_ready&disp_cache_start!=disp_cache_end)begin
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ascii_data<=disp_write_cache[disp_cache_start];
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disp_cache_start<=disp_cache_start+6'd1;
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disp_cache_start<=disp_cache_start+7'd1;
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ascii_data_write_req<=1;
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ascii_state<=1'b1;
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end
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@ -19,7 +19,7 @@
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/* This warning is because we don't use the full address bus. */
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/* verilator lint_off UNUSEDSIGNAL */
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module doublemem(input [19:0] address,output [15:0] cpu_read_data ,input [15:0] cpu_write_data,input rd,input wr,input BHE,input cs);
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module doublemem(input [19:0] address,output [15:0] cpu_read_data ,input [15:0] cpu_write_data,input rd,input wr,input BHE,input cs,input clock);
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/* verilator lint_on UNUSEDSIGNAL */
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reg [15:0] memory [0:`BUILTIN_RAM];
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@ -58,8 +58,8 @@ assign cpu_read_data[15:8] = !BHE & !rd & !cs ? (address[15:4]==12'b1111
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`endif
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always @(negedge wr) begin
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if( cs == 0 ) begin
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always @(posedge clock) begin
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if( cs == 0 && wr == 0) begin
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if(BHE==0)
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memory[address[16:1]][7:0]<=cpu_write_data[15:8];
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if(address[0]==0)
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@ -121,62 +121,6 @@ always @(posedge clock) begin
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in_data_ready<=1;
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end
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end
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////////////////////////////////////////////////
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/* TODO: These are unreachable states but from
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* what i assume to be a bug in yosys. They need
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* to be here for brainfuck_compiled.asm to work.
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* Specifically for the compiled program to not output
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* random characters.
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*/
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8'd14:begin
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data<=4'hf;
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next_line<=1;
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if(!done_writing)begin
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driver_state<=8'd1;
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write_req<=1'b0;
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end else
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write_req<=1'b1;
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end
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8'd13:begin
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data<=4'hf;
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if(!done_writing)begin
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driver_state<=8'd1;
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write_req<=1'b0;
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end else
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write_req<=1'b1;
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end
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8'd1:begin
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if(done_writing==1)
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driver_state<=8'd2;
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end
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8'd2:begin
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data<=4'hE;
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if(!done_writing)begin
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driver_state<=8'd3;
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write_req<=1'b0;
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end else
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write_req<=1'b1;
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end
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8'd3:begin
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if(done_writing==1)
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driver_state<=8'd4;
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end
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8'd4:begin
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data<=4'h0;
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cmd_data<=1'b0;
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if(!done_writing)begin
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driver_state<=8'd5;
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write_req<=1'b0;
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end else
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write_req<=1'b1;
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end
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8'd5:begin
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if(done_writing==1)
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driver_state<=8'd6;
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end
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////////////////////////////////////////////////
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8'd6:begin
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if(next_line)begin
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case(line)
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@ -194,7 +194,8 @@ register_file register_file(
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/* READ 1 */ .read_port1_addr(reg_read_port1_addr),
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/* */ .read_port1_data(reg_read_port1_data),
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/* READ 2 */ .read_port2_addr(DE_reg_read_port2_addr),
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/* */ .read_port2_data(reg_read_port2_data)
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/* */ .read_port2_data(reg_read_port2_data),
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/* GENERAL */ .clock(clock)
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);
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/*############################################################################### */
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@ -21,7 +21,8 @@
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/* Register address format:
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* [W-bit] [ 3-bit address] */
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module register_file (write_port1_addr,write_port1_data,write_port1_we,read_port1_addr,read_port1_data,read_port2_addr,read_port2_data);
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module register_file (write_port1_addr,write_port1_data,write_port1_we,read_port1_addr,read_port1_data,read_port2_addr,read_port2_data,clock);
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input clock;
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input [3:0] write_port1_addr;
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input [3:0] read_port1_addr;
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input [3:0] read_port2_addr;
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@ -48,47 +49,48 @@ assign read_port2_data[7:0] = ( read_port2_addr[3:3] ? registers[read_port2_addr
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wire write_Wbit;
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assign write_Wbit=write_port1_addr[3:3];
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always @(negedge write_port1_we) begin
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if(write_Wbit==1)begin
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/* Word : AX,CX,DX,BX,SP,BP,SI,DI */
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registers[write_port1_addr[2:0]] <= write_port1_data;
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end else begin
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/* Byte : AL,CL,DL,BL,AX,CX,DX,BX */
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if(write_port1_addr[2:2]==1)begin
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/* Byte */
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registers[ {1'b0,write_port1_addr[1:0]} ][15:8] <= write_port1_data[7:0];
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always @(posedge clock) begin
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if(write_port1_we==0)begin
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if(write_Wbit==1)begin
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/* Word : AX,CX,DX,BX,SP,BP,SI,DI */
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registers[write_port1_addr[2:0]] <= write_port1_data;
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end else begin
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/* Byte */
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registers[ {1'b0,write_port1_addr[1:0]} ][7:0] <= write_port1_data[7:0];
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/* Byte : AL,CL,DL,BL,AX,CX,DX,BX */
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if(write_port1_addr[2:2]==1)begin
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/* Byte */
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registers[ {1'b0,write_port1_addr[1:0]} ][15:8] <= write_port1_data[7:0];
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end else begin
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/* Byte */
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registers[ {1'b0,write_port1_addr[1:0]} ][7:0] <= write_port1_data[7:0];
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end
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end
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`ifdef DEBUG_REG_WRITES
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// Icarus Verilog really doesn't like non-blocking assignments
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// here
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/* verilator lint_off BLKSEQ */
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if(write_port1_addr[3:2]==2'b11)begin
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case(write_port1_addr[1:0])
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2'b00: debug_name="sp";
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2'b01: debug_name="bp";
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2'b10: debug_name="si";
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2'b11: debug_name="di";
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endcase
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end else begin
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case(write_port1_addr[1:0])
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2'b00: debug_name="ax";
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2'b01: debug_name="cx";
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2'b10: debug_name="dx";
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2'b11: debug_name="bx";
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endcase
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end
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/* verilator lint_on BLKSEQ */
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if (write_Wbit)
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debug_address<=write_port1_addr[2:0];
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else
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debug_address<={1'b0,write_port1_addr[1:0]};
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`endif
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end
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`ifdef DEBUG_REG_WRITES
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// Icarus Verilog really doesn't like non-blocking assignments
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// here
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/* verilator lint_off BLKSEQ */
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if(write_port1_addr[3:2]==2'b11)begin
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case(write_port1_addr[1:0])
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2'b00: debug_name="sp";
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2'b01: debug_name="bp";
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2'b10: debug_name="si";
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2'b11: debug_name="di";
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endcase
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end else begin
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case(write_port1_addr[1:0])
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2'b00: debug_name="ax";
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2'b01: debug_name="cx";
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2'b10: debug_name="dx";
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2'b11: debug_name="bx";
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endcase
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end
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/* verilator lint_on BLKSEQ */
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if (write_Wbit)
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debug_address<=write_port1_addr[2:0];
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else
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debug_address<={1'b0,write_port1_addr[1:0]};
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`endif
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end
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`ifdef DEBUG_REG_WRITES
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@ -49,7 +49,7 @@ processor p(
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`endif
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);
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doublemem sysmem(address_bus,data_bus_read_,data_bus_write_,rd,wr,BHE,IOMEM);
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doublemem sysmem(address_bus,data_bus_read_,data_bus_write_,rd,wr,BHE,IOMEM,clock);
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`ifdef OUTPUT_JSON_STATISTICS
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string stats_name,version,commit;
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Block a user