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Updated progress on README

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(Tim) Efthimis Kritikos 2023-11-06 08:18:19 +00:00
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@ -13,7 +13,7 @@ A CPU that aims to be binary compatible with the 8086 ISA, focused on optimisati
* [X] Is pipelined
* [ ] Is Out of Order
* [ ] Is superscalar
* [ ] Has been successfully synthesized
* [X] Has been successfully synthesized
### Simulating it
Both Verilator and Icarus Verilog can be used for simulation. You can select which one you want with the SIM variable on [common.mk](./common.mk)