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Fixed a "combinatorial loop" and now if the build-in memory is reduced the design can be synthesized!

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(Tim) Efthimis Kritikos 2023-11-06 05:36:04 +00:00
parent 5ebd53b11c
commit 30ffa1b00c
2 changed files with 17 additions and 13 deletions
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4
system/biu.v
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@ -286,8 +286,10 @@ always @(posedge clock) begin
end
endcase
end
end
/**** UPDATE VALID_INSTRUCTION ****/
/* update VALID_INSTRUCTION and INSTRUCTION */
always @( posedge clock) begin
if(jump_req==1)begin
VALID_INSTRUCTION <= 0;

26
system/decoder.v
View File

@ -76,7 +76,7 @@ wire [`EXEC_STATE_BITS-1:0] next_state;
wire [`ERROR_BITS-1:0] ERROR;
instruction_decode instruction_decode(
/* INPUT */ IF2DE_INSTRUCTION,{8'h0,EX2DE_FLAGS}
/* INPUT */ IF2DE_INSTRUCTION,{8'h0,EX2DE_FLAGS}, clock
/* MICROCODE */ ,ucode_seq_addr_entry,SIMPLE_MICRO,ucode_seq_addr
/* OUTPUT */ ,DEPENDS_ON_PREVIOUS, set_params, MEM_OR_IO,ERROR, HALT
@ -101,10 +101,8 @@ reg owe_set_init;
//TODO: Why do we need to make a local copy on a register for the code inside the always @(next_state) to read it?
// For some reason the raw VALID_INSTRUCTION signal reads always 1 and it has something to do with the block
// being triggered by next_exec
reg VALID_INSTRUCTION_lc;
always @(VALID_INSTRUCTION)begin VALID_INSTRUCTION_lc<=VALID_INSTRUCTION; end
reg wait_;
reg [1:0] wait_;
always @(posedge clock)begin
if(reset==0)begin
@ -122,12 +120,7 @@ always @(posedge clock)begin
VALID_INSTRUCTION_ACK <= 0;
wait_<=0;
end else begin
if(wait_!=0) begin
set_initial_values <= 0;
wait_<=0;
VALID_INSTRUCTION_ACK<=0;
end else if(next_exec==1'b1)begin
if ( ( VALID_INSTRUCTION_lc == 1 || SIMPLE_MICRO == 1 ) /*&& DEPENDS_ON_PREVIOUS == 0 && ucode_seq_addr_entry==`UCODE_NO_INSTRUCTION*/) begin
if(wait_==2) begin
//`define LATCH(VAR) VAR_LATCHED <= VAR; //TODO would this work?
IN_MOD_LATCHED <= IN_MOD;
OUT_MOD_LATCHED <= OUT_MOD;
@ -183,6 +176,13 @@ always @(posedge clock)begin
end
end
end
end else if(wait_!=0) begin
set_initial_values <= 0;
wait_<=0;
VALID_INSTRUCTION_ACK<=0;
end else if(next_exec==1'b1)begin
if ( ( VALID_INSTRUCTION == 1 || SIMPLE_MICRO == 1 ) /*&& DEPENDS_ON_PREVIOUS == 0 && ucode_seq_addr_entry==`UCODE_NO_INSTRUCTION*/) begin
wait_<=2;
end else
valid_exec_data<=0;
end else
@ -225,7 +225,9 @@ assign DATA=ucode_rom[ADDR];
endmodule
module instruction_decode(
/* INPUTS */ input wire [31:0] INSTRUCTION,input wire [15:0] FLAGS
/* verilator lint_off UNUSEDSIGNAL */
/* INPUTS */ input wire [31:0] INSTRUCTION,input wire [15:0] FLAGS,input clock
/* verilator lint_on UNUSEDSIGNAL */
/* MICROCODE */ ,output reg [`UCODE_ADDR_BITS-1:0] seq_addr_entry, input wire SIMPLE_MICRO, input wire [`UCODE_ADDR_BITS-1:0] seq_addr_input
/* OUTPUT */ ,output reg DEPENDS_ON_PREVIOUS, output reg set_params,output reg MEM_OR_IO, output reg [`ERROR_BITS-1:0] ERROR, output reg HALT
@ -272,7 +274,7 @@ reg Sbit,opcode_size;
// then branching off of that instead of the raw bits. otherwise the code
// would be identical
/* verilator lint_off BLKSEQ */
always @( FLAGS or INSTRUCTION or SIMPLE_MICRO or seq_addr_input ) begin
always @( posedge clock ) begin
set_params = 1;
PARAM_ACTION = `NO_LOAD;
Sbit=0;//TODO: If no Sbit we assume it's 0,right?