Removed some code that wasn't meant for synthesis and fixed important bug in Makefile

This commit is contained in:
(Tim) Efthimis Kritikos 2023-11-02 22:19:15 +00:00
parent 601397b7f0
commit 08aac5c7b6
3 changed files with 65 additions and 54 deletions

View File

@ -64,7 +64,7 @@ else
$(error invalid ECP5 device ${ECP5_DEVICE})
endif
ECP5_TARGETS=synth_ecp5.json synth_ecp5_out.config synth_ecp5.bit synth_ecp5.dfu fpga_config/${FPGA_BOARD}/fpga_top.v
ECP5_TARGETS=synth_ecp5.json synth_ecp5_out.config synth_ecp5.bit synth_ecp5.dfu
ECP5_TARGETS+=abc.history # created from yosys
synth_ecp5.json: ${SOURCES} ${TOP_LEVEL_SOURCE} fpga_config/${FPGA_BOARD}/fpga_top.v ${INCLUDES} boot_code.txt

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@ -47,6 +47,13 @@
/********** Internal **********/
`ifdef SYNTHESIS
`undef DEBUG_REG_WRITES
`undef DEBUG_PC_ADDRESS
`undef DEBUG_DATA_READ_WRITES
`undef CALCULATE_IPC
`undef OTUPUT_JSON_STATISTICS
`endif
`ifdef OTUPUT_JSON_STATISTICS
`define CALCULATE_IPC

View File

@ -102,10 +102,12 @@ always @(negedge clock)begin
end
`endif
`ifndef SYNTHESIS
always @(negedge wr) begin
if(IOMEM==1'b1 && address_bus[7:0]==8'hA5 )
$write("%s" ,data_bus_write[15:8]);
end
`endif
`ifdef CALCULATE_IPC
@ -132,66 +134,68 @@ end
`ifdef OTUPUT_JSON_STATISTICS
reg [128:0] instruction_count_temp;
`endif
always @(posedge clock) begin
/* Allow some clock cycles for the waveform*/
case(finish)
2'd0: begin end
2'd1: begin
finish <= 2;
/* instruction_count gets updated at the sme time as HALT is pulled so wait a clock cycle to get an accurate reading*/
$display("\x1b[7mProcessor halted.\nCycles run for : %0d\x1b[m",cycles);
`ifdef CALCULATE_IPC
/* verilator lint_off REALCVT */
$display("\x1b[7mInstr. per cycle : %f\x1b[m", $itor(instruction_count) / $itor(cycles) );
/* verilator lint_on REALCVT */
`endif
`ifdef OTUPUT_JSON_STATISTICS
instruction_count_temp <= instruction_count;
`endif
end
2'd2: begin
finish <= 3;
`ifdef OTUPUT_JSON_STATISTICS
if(json_file_descriptor!=0)
$fdisplay(json_file_descriptor,"],\n\"Total Cycles\":%0d,\n\"Instructions run\":%0d\n}",cycles-1,instruction_count_temp);
`endif
end
2'd3: begin
`ifndef SYNTHESIS
$finish;
`endif
end
endcase
end
always @(posedge reset)begin
sane<=1;
end
reg sane;
always @( ERROR ) begin
if ( ERROR != `ERR_NO_ERROR && sane == 1 ) begin
$display("PROCESSOR RUN INTO AN ERROR.");
case (ERROR)
default:begin
`ifndef SYNTHESIS
reg sane;
reg [128:0] cycles;
always @(posedge reset)begin
sane<=1;
end
always @(posedge clock) begin
/* Allow some clock cycles for the waveform*/
case(finish)
2'd0: begin end
2'd1: begin
finish <= 2;
/* instruction_count gets updated at the sme time as HALT is pulled so wait a clock cycle to get an accurate reading*/
$display("\x1b[7mProcessor halted.\nCycles run for : %0d\x1b[m",cycles);
`ifdef CALCULATE_IPC
/* verilator lint_off REALCVT */
$display("\x1b[7mInstr. per cycle : %f\x1b[m", $itor(instruction_count) / $itor(cycles) );
/* verilator lint_on REALCVT */
`endif
`ifdef OTUPUT_JSON_STATISTICS
instruction_count_temp <= instruction_count;
`endif
end
`ERR_UNIMPL_INSTRUCTION:begin
$display("Unimplemented instruction");
2'd2: begin
finish <= 3;
`ifdef OTUPUT_JSON_STATISTICS
if(json_file_descriptor!=0)
$fdisplay(json_file_descriptor,"],\n\"Total Cycles\":%0d,\n\"Instructions run\":%0d\n}",cycles-1,instruction_count_temp);
`endif
end
`ERR_UNIMPL_ADDRESSING_MODE: begin
$display("Unimplemented addressing mode");
2'd3: begin
$finish;
end
endcase
$display("Cycles run for: %0d",cycles-1);
`ifndef SYNTHESIS
if($value$plusargs("MEMDUMP=%s",memdump_name))begin
$writememh(memdump_name, system.sysmem.memory,0,32767);
end
`endif
finish<=2'd1;
end
end
reg [128:0] cycles;
always @( ERROR ) begin
if ( ERROR != `ERR_NO_ERROR && sane == 1 ) begin
$display("PROCESSOR RUN INTO AN ERROR.");
case (ERROR)
default:begin
end
`ERR_UNIMPL_INSTRUCTION:begin
$display("Unimplemented instruction");
end
`ERR_UNIMPL_ADDRESSING_MODE: begin
$display("Unimplemented addressing mode");
end
endcase
$display("Cycles run for: %0d",cycles-1);
if($value$plusargs("MEMDUMP=%s",memdump_name))begin
$writememh(memdump_name, system.sysmem.memory,0,32767);
end
finish<=2'd1;
end
end
`endif
always @(negedge clock)begin
if(reset==1)