Removed some code that wasn't meant for synthesis and fixed important bug in Makefile
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601397b7f0
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08aac5c7b6
@ -64,7 +64,7 @@ else
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$(error invalid ECP5 device ${ECP5_DEVICE})
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endif
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ECP5_TARGETS=synth_ecp5.json synth_ecp5_out.config synth_ecp5.bit synth_ecp5.dfu fpga_config/${FPGA_BOARD}/fpga_top.v
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ECP5_TARGETS=synth_ecp5.json synth_ecp5_out.config synth_ecp5.bit synth_ecp5.dfu
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ECP5_TARGETS+=abc.history # created from yosys
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synth_ecp5.json: ${SOURCES} ${TOP_LEVEL_SOURCE} fpga_config/${FPGA_BOARD}/fpga_top.v ${INCLUDES} boot_code.txt
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@ -47,6 +47,13 @@
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/********** Internal **********/
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`ifdef SYNTHESIS
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`undef DEBUG_REG_WRITES
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`undef DEBUG_PC_ADDRESS
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`undef DEBUG_DATA_READ_WRITES
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`undef CALCULATE_IPC
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`undef OTUPUT_JSON_STATISTICS
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`endif
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`ifdef OTUPUT_JSON_STATISTICS
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`define CALCULATE_IPC
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110
system/system.v
110
system/system.v
@ -102,10 +102,12 @@ always @(negedge clock)begin
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end
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`endif
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`ifndef SYNTHESIS
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always @(negedge wr) begin
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if(IOMEM==1'b1 && address_bus[7:0]==8'hA5 )
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$write("%s" ,data_bus_write[15:8]);
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end
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`endif
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`ifdef CALCULATE_IPC
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@ -132,66 +134,68 @@ end
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`ifdef OTUPUT_JSON_STATISTICS
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reg [128:0] instruction_count_temp;
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`endif
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always @(posedge clock) begin
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/* Allow some clock cycles for the waveform*/
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case(finish)
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2'd0: begin end
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2'd1: begin
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finish <= 2;
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/* instruction_count gets updated at the sme time as HALT is pulled so wait a clock cycle to get an accurate reading*/
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$display("\x1b[7mProcessor halted.\nCycles run for : %0d\x1b[m",cycles);
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`ifdef CALCULATE_IPC
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/* verilator lint_off REALCVT */
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$display("\x1b[7mInstr. per cycle : %f\x1b[m", $itor(instruction_count) / $itor(cycles) );
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/* verilator lint_on REALCVT */
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`endif
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`ifdef OTUPUT_JSON_STATISTICS
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instruction_count_temp <= instruction_count;
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`endif
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end
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2'd2: begin
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finish <= 3;
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`ifdef OTUPUT_JSON_STATISTICS
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if(json_file_descriptor!=0)
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$fdisplay(json_file_descriptor,"],\n\"Total Cycles\":%0d,\n\"Instructions run\":%0d\n}",cycles-1,instruction_count_temp);
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`endif
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end
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2'd3: begin
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`ifndef SYNTHESIS
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$finish;
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`endif
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end
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endcase
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end
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always @(posedge reset)begin
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sane<=1;
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end
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reg sane;
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always @( ERROR ) begin
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if ( ERROR != `ERR_NO_ERROR && sane == 1 ) begin
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$display("PROCESSOR RUN INTO AN ERROR.");
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case (ERROR)
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default:begin
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`ifndef SYNTHESIS
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reg sane;
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reg [128:0] cycles;
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always @(posedge reset)begin
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sane<=1;
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end
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always @(posedge clock) begin
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/* Allow some clock cycles for the waveform*/
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case(finish)
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2'd0: begin end
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2'd1: begin
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finish <= 2;
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/* instruction_count gets updated at the sme time as HALT is pulled so wait a clock cycle to get an accurate reading*/
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$display("\x1b[7mProcessor halted.\nCycles run for : %0d\x1b[m",cycles);
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`ifdef CALCULATE_IPC
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/* verilator lint_off REALCVT */
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$display("\x1b[7mInstr. per cycle : %f\x1b[m", $itor(instruction_count) / $itor(cycles) );
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/* verilator lint_on REALCVT */
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`endif
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`ifdef OTUPUT_JSON_STATISTICS
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instruction_count_temp <= instruction_count;
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`endif
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end
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`ERR_UNIMPL_INSTRUCTION:begin
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$display("Unimplemented instruction");
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2'd2: begin
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finish <= 3;
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`ifdef OTUPUT_JSON_STATISTICS
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if(json_file_descriptor!=0)
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$fdisplay(json_file_descriptor,"],\n\"Total Cycles\":%0d,\n\"Instructions run\":%0d\n}",cycles-1,instruction_count_temp);
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`endif
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end
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`ERR_UNIMPL_ADDRESSING_MODE: begin
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$display("Unimplemented addressing mode");
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2'd3: begin
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$finish;
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end
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endcase
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$display("Cycles run for: %0d",cycles-1);
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`ifndef SYNTHESIS
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if($value$plusargs("MEMDUMP=%s",memdump_name))begin
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$writememh(memdump_name, system.sysmem.memory,0,32767);
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end
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`endif
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finish<=2'd1;
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end
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end
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reg [128:0] cycles;
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always @( ERROR ) begin
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if ( ERROR != `ERR_NO_ERROR && sane == 1 ) begin
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$display("PROCESSOR RUN INTO AN ERROR.");
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case (ERROR)
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default:begin
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end
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`ERR_UNIMPL_INSTRUCTION:begin
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$display("Unimplemented instruction");
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end
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`ERR_UNIMPL_ADDRESSING_MODE: begin
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$display("Unimplemented addressing mode");
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end
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endcase
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$display("Cycles run for: %0d",cycles-1);
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if($value$plusargs("MEMDUMP=%s",memdump_name))begin
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$writememh(memdump_name, system.sysmem.memory,0,32767);
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end
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finish<=2'd1;
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end
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end
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`endif
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always @(negedge clock)begin
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if(reset==1)
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