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30c3deca37
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Made the execute unit signal the end of execution by a state change rather than the state of a signal to allow for one cycle instructions
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2023-05-17 11:05:20 +01:00 |
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f914d1ec8f
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Cleaned up processor.v a bit
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2023-05-16 16:29:48 +01:00 |
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97912b1a29
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Fixed bug found by icarus verilog and added outdated notice to README
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2023-05-16 13:59:16 +01:00 |
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bfa576e2a0
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Cleaned up the interface between BIU and the processor
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2023-05-16 13:33:08 +01:00 |
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07d2a80b2e
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Added code to record statistics and a tool to plot them
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2023-05-14 16:06:33 +01:00 |
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df342467c7
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Saved a clock cycle from microcode starts and added info in decode to allow saving a cycle on almost every instruction
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2023-05-13 13:45:15 +01:00 |
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00aa828ddc
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Improved parallelism
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2023-05-13 10:52:44 +01:00 |
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fe0426a77b
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Made execute unit run in parallel with everything else. Still not parallel for most of the time though
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2023-05-13 06:51:35 +01:00 |
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539fb8416b
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Fixed copyright notices, did some major cleanup and bumped README's versions
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2023-05-11 16:28:10 +01:00 |
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a8ab6b2dc7
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Separated the execution unit from decode
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2023-05-11 12:22:49 +01:00 |
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7724e5f383
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Removed deprecated BIU_NEXT_POSITION
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2023-05-10 08:53:29 +01:00 |
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7e612bb701
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made BIU snoop into the processor to deliver new instructions faster and fixed some bugs
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2023-05-10 08:31:14 +01:00 |
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b7bfbd4e33
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Improved BIU performance and debug messages
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2023-05-10 04:05:56 +01:00 |
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da51dd6da7
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First draft of a bus interface unit in an effort to make the CPU pipelined. Currently supports code prefetching
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2023-05-07 13:34:15 +01:00 |
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f4b22951d0
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Cleaned up some pieces of code and fixed a bug
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2023-05-04 00:49:04 +01:00 |
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82baacfd5b
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Fixed race condition giving garbage data on debug register write prints and ordering of reg write and instr fetch debug prints
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2023-03-12 08:55:40 +00:00 |
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11624ca2d2
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Added the OUT instruction to be able to properly address I/O and moved printing logic to a device on the I/O space. Also added IRET which is basically just a RET in this case
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2023-03-09 06:03:13 +00:00 |
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9de83fd7c1
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Added partial support for the software interrupt INT instruction
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2023-03-08 07:26:28 +00:00 |
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ba52ff89e6
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Fixed most problems verilator's linter found
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2023-03-04 06:22:28 +00:00 |
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59ec1b7a15
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Removed remnants of the old memory addressing system
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2023-03-03 20:43:25 +00:00 |
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e1bb98c0f0
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Updated toolchain versions and run project through aspell
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2023-03-03 06:54:33 +00:00 |
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f60084344e
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Overhauled cpu frontend. Made memory byte addressable (necessary), cleaned up state machine and fixed small bug with MOV
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2023-03-03 06:29:06 +00:00 |
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f7d76f1944
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Removed useless state in the state machine and ran the project through aspell
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2023-02-26 02:46:43 +00:00 |
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5af6d720c3
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Fixed ADD again and some memory read logic. Compiler runs the default brainfuck message program!!
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2023-02-24 14:10:07 +00:00 |
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355c673a37
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Added a POP instruction
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2023-02-24 11:31:15 +00:00 |
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abee49d6c3
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Implemented PUSH instruction, fixed register addressing bug and a RET bug
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2023-02-24 07:32:27 +00:00 |
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a189da249c
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Added STOS instruction. Native brainfuck compiler started generating code!
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2023-02-24 05:01:55 +00:00 |
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e684db8348
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Added support to CMP for compare memory to opcode parameter, added support for both PROC_DE_LOAD_?_PARAM and PROC_MEMIO_READ at the same command and associated changes
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2023-02-24 02:18:48 +00:00 |
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c4ac55d4c3
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Implemented the RET instruction,fixed CALL bug, clarified MOD naming and usage
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2023-02-23 14:48:48 +00:00 |
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7fde422341
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Added Microcode support, Stack, implemented the CALL instruction in microcode and grouped the wires on the decoder module
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2023-02-22 01:28:23 +00:00 |
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e6c9c722e3
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Run the project through aspell and tweaked the README
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2023-02-19 00:52:52 +00:00 |
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fd4a9b5442
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Fixed register addressing bug, mem read endianness, cleaned up code and added a provisional project logo
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2023-02-19 00:20:53 +00:00 |
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82bd859874
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Moved the decoding of opcodes into a separate module and optimised memory reads
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2023-02-17 18:08:09 +00:00 |
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ded47555a5
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Improved build system and project directory structure
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2023-02-16 01:52:02 +00:00 |
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