500 lines
14 KiB
Verilog
500 lines
14 KiB
Verilog
/* processor.v - implementation of most functions of the 9086 processor
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This file is part of the 9086 project.
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Copyright (c) 2023 Efthymios Kritikos
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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`include "proc_state_def.v"
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`include "alu_header.v"
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`include "config.v"
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module mux4 (in1,in2,in3,in4, sel,out);
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input [0:1] sel;
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parameter WIDTH=16;
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input [WIDTH-1:0] in1,in2,in3,in4;
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output [WIDTH-1:0] out;
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assign out = (sel == 'b00) ? in1 :
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(sel == 'b01) ? in2 :
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(sel == 'b10) ? in3 :
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in4;
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endmodule
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module processor ( input clock, input reset, output reg [19:0] external_address_bus, inout [15:0] external_data_bus,output reg read, output reg write, output reg HALT,output reg ERROR);
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/*if we don't read, output the register to have the bus stable by the write falling edge*/
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reg [15:0] data_bus_output_register;
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assign external_data_bus=read?data_bus_output_register:'hz;
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/*** Global Definitions ***/
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// State
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reg [`PROC_STATE_BITS-1:0] state;
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/* Decoder */
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wire Wbit, Sbit, unaligning_instruction;
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wire [`PROC_STATE_BITS-1:0] next_state;
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wire [1:0]MOD;
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wire [2:0]RM;
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wire [15:0]DE_PARAM1;
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wire [15:0]DE_PARAM2;
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wire DE_ERROR,DE_HALT;
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wire [3:0]DE_reg_read_port1_addr,DE_reg_write_addr;
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wire opcode_size;
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wire has_operands;
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decoder decoder(
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CIR,FLAGS,Wbit,Sbit,unaligning_instruction,opcode_size,DE_ERROR,next_state
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,MOD,RM,DE_PARAM1,DE_PARAM2,DE_HALT,has_operands
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,in_alu1_sel1,in_alu1_sel2,out_alu1_sel
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,DE_reg_read_port1_addr,DE_reg_write_addr
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,ALU_1OP
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);
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// Registers
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reg [19:0] ProgCount; /*TODO consider having single circuit to increment PC instead of having possible lots of adders all over the code*/
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reg [15:0] CIR;
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reg [15:0] PARAM1;
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reg [15:0] PARAM2;
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reg one_byte_instruction;
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reg unaligned_access;
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reg [15:0]FLAGS;
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/* . . . . O D I T S Z . A . P . C */
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// C - Carry flag : carry out or borrow into the high order bit (8bit/16bit)
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//
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// P - Parity flag : is set if result has even parity
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//
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// A - Auxiliary flag : carry out from the low nibble to the high nibble or
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// an equiv borrow. Used by decimal arithmetic instructions
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//
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// Z - Zero flag : Set when result of Operation is zero
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//
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// S - Sign flag : set if the high order bit of the result is 1. aka the sign
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// of the result
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//
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// T - Trap flag : Set the CPU into single step mode where it generates an
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// interrupt after each instruction
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//
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// I - Interrupt flag : 0: interrupts are masked
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//
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// D - Direction flag : 1: string instructions decrement 0: they increment
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//
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// O - Overflow flag : set on arithmetic overflow
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reg [15:0] BYTE_WRITE_TEMP_REG;//we read 16bits here if we want to change just 8 and leave the rest
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/*** RESET LOGIC ***/
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always @(negedge reset) begin
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if (reset==0) begin
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@(posedge clock);
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state=`PROC_HALT_STATE;
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ProgCount=0;//TODO: Reset Vector
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HALT=0;
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reg_write_we=1;
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unaligned_access=0;
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ALU_1OE=1;
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@(posedge reset)
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@(negedge clock);
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state=`PROC_IF_STATE_ENTRY;
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one_byte_instruction=0;
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ERROR=0;
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end
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end
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/*** ALU and EXEC stage logic ***/
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//Architectural Register file
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reg [3:0] reg_write_addr;
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wire [15:0] reg_write_data;
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reg reg_write_we;
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reg [3:0] reg_read_port1_addr;
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reg [15:0] reg_read_port1_data;
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reg [1:0] reg_write_in_sel;
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mux4 #(.WIDTH(16)) REG_FILE_WRITE_IN_MUX(
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ALU_1O,
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16'hz,
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16'hz,
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16'hz,
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reg_write_in_sel,
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reg_write_data);
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register_file register_file(reg_write_addr,reg_write_data,reg_write_we,reg_read_port1_addr,reg_read_port1_data);
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/**** ALU 1 ******/
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reg [1:0] in_alu1_sel1;
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reg [1:0] in_alu1_sel2;
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/* out_alu1_sel : { EXTRA_FUNCTIONS_BIT[0:0], MOD_OR_EXTRA_FUNCTION[1:0] } */
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reg [2:0] out_alu1_sel;
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mux4 #(.WIDTH(16)) MUX16_1A(
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PARAM1,
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reg_read_port1_data,
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{ProgCount[14:0],unaligned_access},
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16'b0,
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in_alu1_sel1,
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ALU_1A);
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mux4 #(.WIDTH(16)) MUX16_1B(
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PARAM2,
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reg_read_port1_data,
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{ProgCount[14:0],unaligned_access},
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16'b0,
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in_alu1_sel2,
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ALU_1B);
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wire [15:0] ALU_1A;
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wire [15:0] ALU_1B;
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wire [15:0] ALU_1O;
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reg [`ALU_OP_BITS-1:0]ALU_1OP;
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reg ALU_1OE;
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wire [7:0] ALU_1FLAGS;
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ALU ALU1(ALU_1A,ALU_1B,ALU_1OE,ALU_1O,ALU_1OP,ALU_1FLAGS,Wbit);
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/*** Processor stages ***/
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`define invalid_instruction state=`PROC_IF_STATE_ENTRY;ERROR=1;
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always @(negedge clock) begin
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case(state)
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`PROC_IF_WRITE_CIR:begin
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if(unaligned_access)begin
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if(one_byte_instruction==1)begin /*TODO: have a read buffer so we can do this even with data reads */
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CIR <= {CIR[7:0],external_data_bus[15:8]};
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state=`PROC_DE_STATE_ENTRY;
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end else begin
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CIR[15:8] <= external_data_bus[7:0];
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state=`PROC_IF_STATE_EXTRA_FETCH_SET;
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end
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end else begin
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CIR <= external_data_bus;
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ProgCount=ProgCount+1;
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state=`PROC_DE_STATE_ENTRY;
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end
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end
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`PROC_IF_STATE_EXTRA_FETCH:begin
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CIR[7:0] <= external_data_bus[15:8];
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state=`PROC_DE_STATE_ENTRY;
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ALU_1OE=0;
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end
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`PROC_EX_STATE_EXIT:begin
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unaligned_access=unaligning_instruction^unaligned_access;
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case(out_alu1_sel) /*TODO: use RM*/
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3'b000,
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3'b001,
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3'b010 : begin
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case (RM) /* Duplicate code with write... */
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3'b000:begin
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/*[BX]+[SI]*/
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`invalid_instruction
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end
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3'b001:begin
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/*[BX]+[SI]*/
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`invalid_instruction
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end
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3'b010:begin
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/*[BP]+[SI]*/
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`invalid_instruction
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end
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3'b011:begin
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/*[BP]+[DI]*/
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`invalid_instruction
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end
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3'b100:begin
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/*[SI]*/
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reg_read_port1_addr=4'b1110;
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state=`PROC_MEMIO_WRITE;
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end
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3'b101:begin
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/*[DI]*/
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reg_read_port1_addr=4'b1111;
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state=`PROC_MEMIO_WRITE;
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end
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3'b110:begin
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/*d16 */
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`invalid_instruction
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end
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3'b111:begin
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/*[BX]*/
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reg_read_port1_addr=4'b1011;
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state=`PROC_MEMIO_WRITE;
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end
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endcase
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end
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3'b011:begin
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reg_write_we=0;
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state=`PROC_IF_STATE_ENTRY;
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end
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3'b101:begin
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ProgCount=ALU_1O[15:1];
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unaligned_access=ALU_1O[0:0];
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state=`PROC_IF_STATE_ENTRY;
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end
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3'b100:begin
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state=`PROC_IF_STATE_ENTRY;
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end
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default:begin
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`invalid_instruction
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end
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endcase
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end
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`PROC_DE_LOAD_16_EXTRA_FETCH_SET:begin
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external_address_bus = ProgCount;
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state=`PROC_DE_LOAD_16_EXTRA_FETCH;
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end
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`PROC_MEMIO_READ_SETADDR:begin
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external_address_bus = {1'b0,reg_read_port1_data[15:1]};
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state=reg_read_port1_data[0:0]?`PROC_MEMIO_GET_UNALIGNED_DATA:`PROC_MEMIO_GET_ALIGNED_DATA;
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end
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`PROC_MEMIO_PUT_BYTE:begin
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BYTE_WRITE_TEMP_REG=external_data_bus;
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state=`PROC_MEMIO_PUT_BYTE_STOP_READ;
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end
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`PROC_MEMIO_WRITE_EXIT:begin
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write=0;
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state=`PROC_IF_STATE_ENTRY;
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end
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`PROC_MEMIO_PUT_ALIGNED_DATA:begin
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read=1;
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data_bus_output_register={ALU_1O[7:0],ALU_1O[15:8]};
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state=`PROC_MEMIO_WRITE_EXIT;
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end
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`PROC_MEMIO_PUT_UNALIGNED_DATA:begin
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BYTE_WRITE_TEMP_REG=external_data_bus;
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state=`PROC_MEMIO_PUT_UNALIGNED_FIRST_BYTE;
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end
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`PROC_MEMIO_PUT_UNALIGNED_PREP_NEXT:begin
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write=0;
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state=`PROC_MEMIO_PUT_UNALIGNED_PREP_NEXT2;
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data_bus_output_register={BYTE_WRITE_TEMP_REG[15:8],ALU_1O[7:0]};
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end
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`PROC_MEMIO_PUT_UNALIGNED_PREP_NEXT3:begin
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BYTE_WRITE_TEMP_REG=external_data_bus;
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state=`PROC_MEMIO_PUT_UNALIGNED_PREP_NEXT4;
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end
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`PROC_MEMIO_GET_SECOND_BYTE:begin
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external_address_bus=external_address_bus+1;
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state=`PROC_MEMIO_GET_SECOND_BYTE1;
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end
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`PROC_DE_LOAD_8_PARAM_UNALIGNED:begin
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if({Sbit,Wbit}==2'b11)begin
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PARAM1 = {{8{external_data_bus[15:15]}},external_data_bus[15:8]};
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end else begin
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PARAM1[7:0] = external_data_bus[15:8];
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end
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state=`PROC_EX_STATE_ENTRY;
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end
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endcase
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end
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always @(posedge clock) begin
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case(state)
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`PROC_HALT_STATE:begin
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end
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`PROC_IF_STATE_ENTRY:begin
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`ifdef DEBUG_PC_ADDRESS
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/* Weird (possible bug) where even though the
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* testbench stop the clock after ERROR gets
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* raised the logic for the rising edge still
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* gets triggered printing this debug message. */
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if(ERROR!=1)
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$display("Fetched instruction at %04x",{ProgCount[18:0],unaligned_access});
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`endif
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external_address_bus <= ProgCount;
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read <= 0;
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write <= 1;
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reg_write_we=1;
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ALU_1OE=1;
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state=`PROC_IF_WRITE_CIR;
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reg_write_in_sel=2'b00;
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end
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`PROC_IF_STATE_EXTRA_FETCH_SET:begin
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ProgCount=ProgCount+1;
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external_address_bus <= ProgCount;
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state=`PROC_IF_STATE_EXTRA_FETCH;
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end
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`PROC_DE_STATE_ENTRY:begin
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/* IF we are unaligned, the address bus contains the
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* ProgCount and points to the second word containing
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* the nest unread byte in extenral_data_bus[7:0]. If
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* we are aligned the address bus points to the first
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* word of the instruction which contains no useful
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* data anymore but the ProgCount has the correct
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* address so update it now so that whatever the case
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* external_data_bus contains at leat some unkown data */
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one_byte_instruction=(!has_operands)&&(!opcode_size);
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external_address_bus <= ProgCount;
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state=next_state;
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PARAM1=DE_PARAM1;
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PARAM2=DE_PARAM2;
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ERROR=DE_ERROR;
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HALT=DE_HALT;
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reg_read_port1_addr=DE_reg_read_port1_addr;
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reg_write_addr=DE_reg_write_addr;
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end
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`PROC_DE_LOAD_REG_TO_PARAM:begin
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PARAM1=reg_read_port1_data;
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state=`PROC_EX_STATE_ENTRY;
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end
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`PROC_DE_LOAD_8_PARAM:begin
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if(opcode_size==0)begin
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if({Sbit,Wbit}==2'b11)begin
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/*signed "16bit" read*/
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PARAM1 = {{8{CIR[7:7]}},CIR[7:0]};
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end else begin
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PARAM1[7:0] = CIR[7:0];
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end
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state=`PROC_EX_STATE_ENTRY;
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end else begin
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if(unaligned_access==1)begin
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if({Sbit,Wbit}==2'b11)begin
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/*signed "16bit" read*/
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PARAM1 = {{8{external_data_bus[7:7]}},external_data_bus[7:0]};
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end else begin
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PARAM1[7:0] = external_data_bus[7:0];
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end
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ProgCount=ProgCount+1;
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state=`PROC_EX_STATE_ENTRY;
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end else begin
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external_address_bus=ProgCount;
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state=`PROC_DE_LOAD_8_PARAM_UNALIGNED;
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end
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end
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end
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`PROC_DE_LOAD_16_PARAM:begin
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if(opcode_size==0)begin
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if(unaligned_access==1)begin
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PARAM1 = {external_data_bus[7:0],external_data_bus[15:8]};
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ProgCount=ProgCount+1;
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state=`PROC_EX_STATE_ENTRY;
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end else begin
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PARAM1 = {external_data_bus[15:8],CIR[7:0]};
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state=`PROC_EX_STATE_ENTRY;
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end
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end else begin
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ProgCount=ProgCount+1;
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if(unaligned_access==1)begin
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PARAM1[7:0] = external_data_bus[7:0];
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state=`PROC_DE_LOAD_16_EXTRA_FETCH_SET;
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end else begin
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PARAM1 = {external_data_bus[7:0],external_data_bus[15:8]};
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state=`PROC_EX_STATE_ENTRY;
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end
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end
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end
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`PROC_DE_LOAD_16_EXTRA_FETCH:begin
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PARAM1[15:8] = external_data_bus[15:8];
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state=`PROC_EX_STATE_ENTRY;
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end
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`RPOC_MEMIO_READ:begin
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/*Decode MOD R/M, read the data and place it to PARAM1*/
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case (RM)
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3'b000:begin
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/*[BX]+[SI]*/
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`invalid_instruction
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end
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3'b001:begin
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/*[BX]+[SI]*/
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`invalid_instruction
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end
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3'b010:begin
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/*[BP]+[SI]*/
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`invalid_instruction
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end
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3'b011:begin
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/*[BP]+[DI]*/
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`invalid_instruction
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end
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3'b100:begin
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/*[SI]*/
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reg_read_port1_addr=4'b1110;
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state=`PROC_MEMIO_READ_SETADDR;
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end
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3'b101:begin
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/*[DI]*/
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reg_read_port1_addr=4'b1111;
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state=`PROC_MEMIO_READ_SETADDR;
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end
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3'b110:begin
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/*d16 */
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`invalid_instruction
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end
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3'b111:begin
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/*[BX]*/
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reg_read_port1_addr=4'b1011;
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state=`PROC_MEMIO_READ_SETADDR;
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end
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endcase
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if(MOD!=2'b00)begin
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/*Actually check if 01 and add the 8bits or if 10 add the 16bits ....*/
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`invalid_instruction;
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end
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end
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`PROC_MEMIO_GET_ALIGNED_DATA:begin
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PARAM1=(Wbit==1)? external_data_bus : {8'b00000000,external_data_bus[15:8]} ;
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state=`PROC_EX_STATE_ENTRY;
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end
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`PROC_MEMIO_GET_UNALIGNED_DATA:begin
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PARAM1={8'b00000000,external_data_bus[7:0]};
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if(Wbit==1) begin
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state=`PROC_MEMIO_GET_SECOND_BYTE;
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end else begin
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state=`PROC_EX_STATE_ENTRY;
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end
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end
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`PROC_EX_STATE_ENTRY:begin
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FLAGS[7:0] = ALU_1FLAGS[7:0];
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state=`PROC_EX_STATE_EXIT;
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end
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`PROC_MEMIO_WRITE:begin
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/* ADDRESS: reg_read_port1_data DATA:ALU1_O */
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`ifdef DEBUG_MEMORY_WRITES
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$display("Writing at %04x , %04x",reg_read_port1_data,ALU_1O);
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`endif
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external_address_bus = {1'b0,reg_read_port1_data[15:1]};
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state = (Wbit==0) ? `PROC_MEMIO_PUT_BYTE : (reg_read_port1_data[0:0]?`PROC_MEMIO_PUT_UNALIGNED_DATA:`PROC_MEMIO_PUT_ALIGNED_DATA) ;
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end
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`PROC_MEMIO_PUT_BYTE_STOP_READ:begin
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read=1;
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state=`PROC_MEMIO_WRITE_EXIT;
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if(reg_read_port1_data[0:0]==0)
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data_bus_output_register={ALU_1O[7:0],BYTE_WRITE_TEMP_REG[7:0]};
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else
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data_bus_output_register={BYTE_WRITE_TEMP_REG[15:8],ALU_1O[7:0]};
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end
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`PROC_MEMIO_PUT_UNALIGNED_FIRST_BYTE:begin
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read=1;
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state=`PROC_MEMIO_PUT_UNALIGNED_PREP_NEXT;
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data_bus_output_register={BYTE_WRITE_TEMP_REG[15:8],ALU_1O[7:0]};
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end
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`PROC_MEMIO_PUT_UNALIGNED_PREP_NEXT2:begin
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external_address_bus=external_address_bus+1;
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write=1;
|
|
read=0;
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state=`PROC_MEMIO_PUT_UNALIGNED_PREP_NEXT3;
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end
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`PROC_MEMIO_PUT_UNALIGNED_PREP_NEXT4:begin
|
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read=1;
|
|
state=`PROC_MEMIO_WRITE_EXIT;
|
|
data_bus_output_register={ALU_1O[15:8],BYTE_WRITE_TEMP_REG[7:0]};
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end
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`PROC_MEMIO_GET_SECOND_BYTE1:begin
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PARAM1[15:8]=external_data_bus[15:8];
|
|
state=`PROC_EX_STATE_ENTRY;
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|
end
|
|
endcase
|
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end
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|
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endmodule
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