540 lines
15 KiB
Verilog
540 lines
15 KiB
Verilog
/* processor.v - implementation of most functions of the 9086 processor
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This file is part of the 9086 project.
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Copyright (c) 2023 Efthymios Kritikos
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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`include "proc_state_def.v"
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`include "alu_header.v"
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`include "config.v"
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`include "ucode_header.v"
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`include "error_header.v"
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//HALT: active high
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//IOMEM: 1=IO 0=MEM
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//write: active low
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//read: active low
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//reset: active low
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module processor ( input clock, input reset, output [19:0] external_address_bus, inout [15:0] external_data_bus,output read, output write,output BHE,output IOMEM, output reg HALT,output reg [`ERROR_BITS-1:0] ERROR);
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/*** Global Definitions ***/
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reg [`PROC_STATE_BITS-1:0] state;
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/*############ Bus Interface Unit ############################################### */
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wire [31:0] INSTRUCTION;
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reg jump_req;
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wire VALID_INSTRUCTION;
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wire [15:0] INSTRUCTION_LOCATION;
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reg [15:0] BIU_ADDRESS_INPUT;
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wire [15:0] BIU_DATA;
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reg biu_write_request;
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reg biu_data_direction;
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reg biu_read_request;
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wire BIU_VALID_DATA;
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BIU BIU(
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clock,reset,external_address_bus,external_data_bus,read,write,BHE,IOMEM,
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INSTRUCTION,VALID_INSTRUCTION,INSTRUCTION_LOCATION,jump_req,BIU_ADDRESS_INPUT,BIU_DATA,biu_write_request,biu_read_request,Wbit,BIU_VALID_DATA,MEM_OR_IO,
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state,SIMPLE_MICRO
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);
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assign BIU_DATA= biu_data_direction ? 16'hz : (memio_address_select?reg_read_port1_data:ALU_1O);
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/*############ Decoder ########################################################## */
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reg Wbit, Sbit, opcode_size;
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wire DE_Wbit, DE_Sbit, DE_opcode_size;
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wire [`PROC_STATE_BITS-1:0] next_state;
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reg [2:0]RM;
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wire [15:0]DE_PARAM1;// Input param1 form decoder to alu
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wire [15:0]DE_PARAM2;
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wire [2:0]DE_IN_MOD;
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wire [2:0]DE_RM;
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wire [2:0]DE_OUT_MOD;
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wire [`ERROR_BITS-1:0] DE_ERROR;
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wire DE_HALT;
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wire [3:0]DE_reg_read_port1_addr,DE_reg_write_addr,DE_reg_read_port2_addr;
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wire [11:0]DE_REGISTER_CONTROL;
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wire [2:0]INSTRUCTION_INFO;
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wire [`ERROR_BITS:0]DECODER_SIGNALS;
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wire [`UCODE_ADDR_BITS-1:0] ucode_seq_addr_entry;
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reg SIMPLE_MICRO; /* output simple decodings (=0) or microcode data (=1) */
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wire [2:0] DE_instruction_size;
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reg instruction_size_init;
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//TODO : remove completely?
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/* verilator lint_off UNUSEDSIGNAL */
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wire [2:0] instruction_size;
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/* verilator lint_on UNUSEDSIGNAL */
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assign instruction_size = instruction_size_init ? 3'b010 : DE_instruction_size;
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reg memio_address_select;
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wire DE_memio_address_select;
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wire DE_MEM_OR_IO;
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reg MEM_OR_IO;
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wire [1:0] DE_in_alu1_sel1;
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wire [1:0] DE_in_alu1_sel2;
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reg [`ALU_OP_BITS-1:0] DE_ALU_1OP;
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decoder decoder(
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.CIR(INSTRUCTION[31:16]),
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.FLAGS(FLAGS),
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.INSTRUCTION_INFO(INSTRUCTION_INFO),
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.DECODER_SIGNALS(DECODER_SIGNALS),
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.next_state(next_state),
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.IN_MOD(DE_IN_MOD),
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.RM(DE_RM),
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.PARAM1(DE_PARAM1),
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.PARAM2(DE_PARAM2),
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.in_alu1_sel1(DE_in_alu1_sel1),
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.in_alu1_sel2(DE_in_alu1_sel2),
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.OUT_MOD(DE_OUT_MOD),
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.REGISTER_FILE_CONTROL(DE_REGISTER_CONTROL),
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.ALU_1OP(DE_ALU_1OP),
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.seq_addr_entry(ucode_seq_addr_entry),
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.SIMPLE_MICRO(SIMPLE_MICRO),
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.seq_addr_input(ucode_seq_addr),
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.instruction_size(DE_instruction_size),
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.memio_address_select(DE_memio_address_select),
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.MEM_OR_IO(DE_MEM_OR_IO)
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);
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assign DE_Wbit=INSTRUCTION_INFO[2:2];
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assign DE_Sbit=INSTRUCTION_INFO[1:1];
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assign DE_opcode_size=INSTRUCTION_INFO[0:0];
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assign DE_reg_write_addr=DE_REGISTER_CONTROL[11:8];
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assign DE_reg_read_port1_addr=DE_REGISTER_CONTROL[7:4];
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assign DE_reg_read_port2_addr=DE_REGISTER_CONTROL[3:0];
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assign DE_HALT=DECODER_SIGNALS[0:0];
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assign DE_ERROR=DECODER_SIGNALS[`ERROR_BITS:1];
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reg [`UCODE_ADDR_BITS-1:0] ucode_seq_addr;
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/*############ REGISTERS ########################################################## */
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reg [15:0] PARAM1;
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reg [15:0] PARAM2;
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// verilator lint_off UNDRIVEN
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reg [15:0] FLAGS;
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// verilator lint_on UNDRIVEN
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//Architectural Register file
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reg [3:0] reg_write_addr;
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wire [15:0] reg_write_data;
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reg reg_write_we;
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reg [3:0] reg_read_port1_addr;
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reg [15:0] reg_read_port1_data;
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reg [3:0] reg_read_port2_addr;
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reg [15:0] reg_read_port2_data;
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reg [1:0] reg_write_in_sel;
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mux4 #(.WIDTH(16)) REG_FILE_WRITE_IN_MUX(
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ALU_1O,
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16'hz,
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16'hz,
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16'hz,
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reg_write_in_sel,
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reg_write_data);
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register_file register_file(
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.write_port1_addr(reg_write_addr),
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.write_port1_data(reg_write_data),
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.write_port1_we(reg_write_we),
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.read_port1_addr(reg_read_port1_addr),
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.read_port1_data(reg_read_port1_data),
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.read_port2_addr(reg_read_port2_addr),
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.read_port2_data(reg_read_port2_data)
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);
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reg [15:0] ProgCount;
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/*############ ALU / Execution units ########################################################## */
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// ALU 1
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reg [1:0] in_alu1_sel1;
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reg [1:0] in_alu1_sel2;
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/* OUT_MOD : { EXTRA_FUNCTIONS_BIT[0:0], MOD_OR_EXTRA_FUNCTION[1:0] } */
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reg [2:0] IN_MOD;
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reg [2:0] OUT_MOD;
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mux4 #(.WIDTH(16)) MUX16_1A(
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/*0*/ PARAM1,
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/*1*/ reg_read_port1_data,
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/*2*/ ProgCount[15:0],
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/*3*/ 16'd0, /*0 Constant*/
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in_alu1_sel1,
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ALU_1A);
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mux4 #(.WIDTH(16)) MUX16_1B(
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/*0*/ PARAM2,
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/*1*/ reg_read_port2_data,
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/*2*/ ProgCount[15:0],
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/*3*/ 16'd0, /*0 Constant*/
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in_alu1_sel2,
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ALU_1B);
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wire [15:0] ALU_1A;
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wire [15:0] ALU_1B;
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wire [15:0] ALU_1O;
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reg [`ALU_OP_BITS-1:0]ALU_1OP;
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wire [7:0] ALU_1FLAGS;
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ALU ALU1(
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.A(ALU_1A),
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.B(ALU_1B),
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.OUT(ALU_1O),
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.op(ALU_1OP),
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.FLAGS(ALU_1FLAGS),
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.Wbit(Wbit)
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);
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/*############ Processor state machine ########################################################## */
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/*** RESET LOGIC ***/
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/* verilator lint_off MULTIDRIVEN */
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always @(negedge reset) begin
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state <= `PROC_HALT_STATE; //TODO: race condition ??
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end
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always @(posedge reset) begin
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state <= `PROC_RESET;
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end
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/* verilator lint_on MULTIDRIVEN */
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/*** Processor stages ***/
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`define unimpl_addressing_mode state <= `PROC_DE_STATE_ENTRY;ERROR <= `ERR_UNIMPL_ADDRESSING_MODE;
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wire [2:0] instr_end;
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InstrSize InstrSize({INSTRUCTION[31:24],INSTRUCTION[21:19]},instr_end);
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reg [23:0] INSTRUCTION_BUFFER;
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always @(posedge clock) begin
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case(state)
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`PROC_RESET:begin
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jump_req <= 0;
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ucode_seq_addr <= `UCODE_NO_INSTRUCTION;
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HALT <= 0;
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ERROR <= `ERR_NO_ERROR;
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SIMPLE_MICRO <= 0;
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reg_write_we <= 1;
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instruction_size_init <= 1;
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state <= `PROC_DE_STATE_ENTRY;
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reg_write_in_sel <= 2'b00; //only got wirtten in IF
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biu_write_request <= 0;
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biu_data_direction <= 0;
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biu_read_request <= 0;
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end
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`PROC_HALT_STATE:begin
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end
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`PROC_DE_STATE_ENTRY:begin
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reg_write_we <= 1;
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if(VALID_INSTRUCTION==1) begin
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if(SIMPLE_MICRO==0)begin
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/*This flag is set at reset and jump because
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* at IF we need to know the size of the
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* previous instruction (specifically if it was
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* a single byte and the value would be
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* incorrect in both cases. So when it gets
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* set reset it only at the start of the next
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* 8086 instruction */
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instruction_size_init <= 0;
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/* We cannot set these directly within
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* microcode so don't overwrite useful values
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* each tie the next microcode is executed.
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* Note this still allows to set initial values
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* at the start of the microcode */
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PARAM1 <= DE_PARAM1;
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PARAM2 <= DE_PARAM2;
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`ifdef DEBUG_PC_ADDRESS
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$display("Running command at %04x (%08x)",INSTRUCTION_LOCATION,INSTRUCTION);
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`endif
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ProgCount <= INSTRUCTION_LOCATION+{12'b0,instr_end};
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INSTRUCTION_BUFFER<=INSTRUCTION[23:0];
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end
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IN_MOD <= DE_IN_MOD;
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OUT_MOD <= DE_OUT_MOD;
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RM <= DE_RM;
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ERROR <= DE_ERROR;
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HALT <= DE_HALT;
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Wbit <= DE_Wbit;
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Sbit <= DE_Sbit;
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opcode_size <= DE_opcode_size;
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memio_address_select<=DE_memio_address_select;
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reg_read_port1_addr <= DE_reg_read_port1_addr;
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reg_read_port2_addr <= DE_reg_read_port2_addr;
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reg_write_addr <= DE_reg_write_addr;
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MEM_OR_IO <= DE_MEM_OR_IO;
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in_alu1_sel1 <= DE_in_alu1_sel1;
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in_alu1_sel2 <= DE_in_alu1_sel2;
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ALU_1OP <= DE_ALU_1OP;
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if ( (ucode_seq_addr==`UCODE_NO_INSTRUCTION) && (ucode_seq_addr_entry!=`UCODE_NO_INSTRUCTION) )begin
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/*switch to microcode decoding*/
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ucode_seq_addr <= ucode_seq_addr_entry;
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SIMPLE_MICRO <= 1;
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/*keep state the same and rerun decode this time with all the data from the microcode rom*/
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jump_req <= 0;
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end else begin
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state <= next_state;
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if ( SIMPLE_MICRO == 0 ) begin
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jump_req <= 0;
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end
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end
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end
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end
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`PROC_DE_LOAD_REG_TO_PARAM:begin
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PARAM2<=reg_read_port2_data;
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case(IN_MOD)
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3'b000,3'b001,3'b010: state <= `PROC_MEMIO_READ;
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default: state <= `PROC_EX_STATE_ENTRY;
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endcase
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end
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`PROC_DE_LOAD_8_PARAM:begin
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if(opcode_size==0)begin
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if({Sbit,Wbit}==2'b11)begin
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/*signed "16bit" read*/
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PARAM1 <= {{8{INSTRUCTION_BUFFER[23:23]}},INSTRUCTION_BUFFER[23:16]};
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end else begin
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PARAM1[7:0] <= INSTRUCTION_BUFFER[23:16];
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end
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case(IN_MOD)
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3'b000,3'b001,3'b010: state <= `PROC_MEMIO_READ;
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default: state <= `PROC_EX_STATE_ENTRY;
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endcase
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end else begin
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if({Sbit,Wbit}==2'b11)begin
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/*signed "16bit" read*/
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PARAM1 <= {{8{INSTRUCTION_BUFFER[15:15]}},INSTRUCTION_BUFFER[15:8]};
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end else begin
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PARAM1[7:0] <= INSTRUCTION_BUFFER[15:8];
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end
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end
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case(IN_MOD)
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3'b000,3'b001,3'b010: state <= `PROC_MEMIO_READ;
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default: state <= `PROC_EX_STATE_ENTRY;
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endcase
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end
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`PROC_DE_LOAD_16_PARAM:begin
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if(opcode_size==0)begin
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PARAM1[7:0] <= INSTRUCTION_BUFFER[23:16];
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PARAM1[15:8] <= INSTRUCTION_BUFFER[15:8];
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end else begin
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PARAM1[15:8] <= INSTRUCTION_BUFFER[7:0];
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PARAM1[7:0] <= INSTRUCTION_BUFFER[15:8];
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end
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case(IN_MOD)
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3'b000,3'b001,3'b010: state <= `PROC_MEMIO_READ;
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default: state <= `PROC_EX_STATE_ENTRY;
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endcase
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end
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`PROC_MEMIO_READ:begin
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/*Decode MOD R/M, read the data and place it to PARAM1*/
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case (IN_MOD)
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3'b000,
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3'b001,
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3'b010:begin
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case (RM)
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3'b000:begin
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/*[BX]+[SI]*/
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`unimpl_addressing_mode
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end
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3'b001:begin
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/*[BX]+[SI]*/
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`unimpl_addressing_mode
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end
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3'b010:begin
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/*[BP]+[SI]*/
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`unimpl_addressing_mode
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end
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3'b011:begin
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/*[BP]+[DI]*/
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`unimpl_addressing_mode
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end
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3'b100:begin
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/*[SI]*/
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reg_read_port1_addr <= 4'b1110;
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state <= `PROC_MEMIO_READ_SETADDR;
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end
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3'b101:begin
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/*[DI]*/
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reg_read_port1_addr <= 4'b1111;
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state <= `PROC_MEMIO_READ_SETADDR;
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end
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3'b110:begin
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/*d16 */
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`unimpl_addressing_mode
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end
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3'b111:begin
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/*[BX]*/
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reg_read_port1_addr <= 4'b1011;
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state <= `PROC_MEMIO_READ_SETADDR;
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end
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endcase
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if(IN_MOD!=3'b000)begin
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/*Actually check if 01 and add the 8bits or if 10 add the 16bits ....*/
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`unimpl_addressing_mode;
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end
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end
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3'b110:begin /* SP Indirect read*/
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reg_read_port1_addr <= 4'b1100;
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state <= `PROC_MEMIO_READ_SETADDR;
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end
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default:begin
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`unimpl_addressing_mode
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end
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endcase
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end
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`PROC_MEMIO_READ_SETADDR:begin
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if(memio_address_select==0)
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BIU_ADDRESS_INPUT <= reg_read_port1_data[15:0];
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else
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BIU_ADDRESS_INPUT <= ALU_1O;
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if ( BIU_VALID_DATA == 1 ) begin
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state <= `PROC_EX_STATE_ENTRY;
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PARAM2 <= BIU_DATA;
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biu_read_request <= 0;
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biu_data_direction <= 0;
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end else begin
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biu_data_direction <= 1;
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biu_read_request <= 1;
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end
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end
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`PROC_NEXT_INSTRUCTION:begin
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/*necessary for biu to see we went on another state from decode to give us a new instruction*/
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state <= `PROC_DE_STATE_ENTRY;
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end
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`PROC_EX_STATE_ENTRY:begin
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FLAGS[7:0] <= ALU_1FLAGS[7:0];
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case(OUT_MOD)
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3'b000,
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3'b001,
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3'b010 : begin
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if(memio_address_select==1)
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state <= `PROC_MEMIO_WRITE;
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else
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case (RM) /* Duplicate code with write... */
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3'b000:begin
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/*[BX]+[SI]*/
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`unimpl_addressing_mode
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end
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3'b001:begin
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/*[BX]+[SI]*/
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`unimpl_addressing_mode
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end
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3'b010:begin
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/*[BP]+[SI]*/
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`unimpl_addressing_mode
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end
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3'b011:begin
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/*[BP]+[DI]*/
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`unimpl_addressing_mode
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end
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3'b100:begin
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/*[SI]*/
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reg_read_port1_addr <= 4'b1110;
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state <= `PROC_MEMIO_WRITE;
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end
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3'b101:begin
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/*[DI]*/
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reg_read_port1_addr <= 4'b1111;
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state <= `PROC_MEMIO_WRITE;
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end
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3'b110:begin
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/*d16 */
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`unimpl_addressing_mode
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end
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3'b111:begin
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/*[BX]*/
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reg_read_port1_addr <= 4'b1011;
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state <= `PROC_MEMIO_WRITE;
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end
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endcase
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end
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3'b011:begin
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reg_write_we <= 0;
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if (ucode_seq_addr==`UCODE_NO_INSTRUCTION)
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state <= `PROC_DE_STATE_ENTRY;
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|
else
|
|
state <= `PROC_NEXT_MICROCODE;
|
|
end
|
|
3'b100:begin /*No output*/
|
|
if (ucode_seq_addr==`UCODE_NO_INSTRUCTION)
|
|
state <= `PROC_DE_STATE_ENTRY;
|
|
else
|
|
state <= `PROC_NEXT_MICROCODE;
|
|
end
|
|
3'b101:begin /* Program Counter*/
|
|
BIU_ADDRESS_INPUT <= ALU_1O[15:0];
|
|
jump_req <= 1;
|
|
instruction_size_init <= 1;
|
|
if (ucode_seq_addr==`UCODE_NO_INSTRUCTION)
|
|
state <= `PROC_DE_STATE_ENTRY;
|
|
else
|
|
state <= `PROC_NEXT_MICROCODE;
|
|
end
|
|
3'b110:begin /* SP Indirect write*/
|
|
reg_read_port1_addr <= 4'b1100;
|
|
state <= `PROC_MEMIO_WRITE;
|
|
end
|
|
3'b111:begin /* Write to PRAM1 (for microcode calculations) */
|
|
PARAM1 <= ALU_1O;
|
|
if (ucode_seq_addr==`UCODE_NO_INSTRUCTION)
|
|
state <= `PROC_DE_STATE_ENTRY;
|
|
else
|
|
state <= `PROC_NEXT_MICROCODE;
|
|
end
|
|
default:begin
|
|
`unimpl_addressing_mode
|
|
end
|
|
endcase
|
|
end
|
|
`PROC_MEMIO_WRITE:begin
|
|
/* if memio_address_select == 0 ADDRESS: reg_read_port1_data DATA:ALU1_O */
|
|
/* if memio_address_select == 1 ADDRESS: ALU1_O DATA: reg_read_port1_data */
|
|
|
|
biu_write_request <= 1;
|
|
|
|
if(memio_address_select==0)
|
|
BIU_ADDRESS_INPUT <= reg_read_port1_data[15:0];
|
|
else
|
|
BIU_ADDRESS_INPUT <= ALU_1O;
|
|
|
|
if (write == 0) begin
|
|
biu_write_request <= 0;
|
|
if (ucode_seq_addr==`UCODE_NO_INSTRUCTION)
|
|
state <= `PROC_DE_STATE_ENTRY;
|
|
else
|
|
state <= `PROC_NEXT_MICROCODE;
|
|
end
|
|
|
|
end
|
|
`PROC_NEXT_MICROCODE:begin
|
|
ucode_seq_addr <= ucode_seq_addr_entry; /*Reused for next address*/
|
|
if( ucode_seq_addr_entry == `UCODE_NO_INSTRUCTION )begin
|
|
/*Finished microcode*/
|
|
SIMPLE_MICRO <= 0;
|
|
end
|
|
state <= `PROC_DE_STATE_ENTRY;
|
|
reg_write_we <= 1;
|
|
end
|
|
default:begin
|
|
end
|
|
endcase
|
|
end
|
|
`undef unimpl_addressing_mode
|
|
|
|
|
|
endmodule
|