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made BIU snoop into the processor to deliver new instructions faster and fixed some bugs

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This commit is contained in:
(Tim) Efthimis Kritikos 2023-05-10 08:31:14 +01:00
parent c854818d6d
commit 7e612bb701
3 changed files with 41 additions and 20 deletions
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44
system/biu.v
View File

@ -41,7 +41,8 @@ module BIU (
/*outside world*/ input clock, input reset, output reg [19:0] external_address_bus,
/* */ inout [15:0] external_data_bus,output reg read, output reg write,output reg BHE,output reg IOMEM,
/* internal */ output reg [31:0] INSTRUCTION, output reg VALID_INSTRUCTION, output reg [15:0] INSTRUCTION_LOCATION, input [1:0] NEXT_POSITION,
/* */ input[15:0] ADDRESS_INPUT, inout [15:0] DATA, input write_request, input read_request, input Wbit, output reg VALID_DATA, input MEM_OR_IO
/* */ input[15:0] ADDRESS_INPUT, inout [15:0] DATA, input write_request, input read_request, input Wbit, output reg VALID_DATA, input MEM_OR_IO,
/* */ input [`PROC_STATE_BITS-1:0] proc_state, input SIMPLE_MICRO
);
reg [15:0] data_bus_output_register;
@ -276,6 +277,7 @@ always @(posedge clock) begin
VALID_INSTRUCTION <= 0;
VALID_DATA <= 0;
DATA_DIR <= 0;
was_dec <= 0;
end
default: begin
biu_state <= `BIU_NEXT_ACTION;/*Should be unreachable*/
@ -291,19 +293,47 @@ wire [2:0] fifoIsize;
wire Isit1;
/* verilator lint_on UNDRIVEN */
`ifdef EARLY_VALID_INSTRUCTION
InstrSize fifoInstrSize({INPUT_FIFO[FIFO_start][7:0],INPUT_FIFO[FIFO_start][5:3]},fifoIsize);
InstrSize fifoInstrSize({INPUT_FIFO[FIFO_start][7:0],INPUT_FIFO[FIFO_start+1][5:3]},fifoIsize);
Is1 Is1(INPUT_FIFO[FIFO_start][7:0],Isit1);
`endif
reg was_dec;
reg was_simple;
always @( proc_state ) begin
case (proc_state)
`PROC_DE_STATE_ENTRY: begin
was_dec<=1;
end
default: begin
if( SIMPLE_MICRO==0 && was_dec==1 )begin
was_dec<=0;
/* verilator lint_off BLKSEQ */
FIFO_start = FIFO_start + {1'b0,Isize};
INSTRUCTION_LOCATION <= INSTRUCTION_LOCATION + {12'b0,Isize};;
/* verilator lint_on BLKSEQ */
VALID_INSTRUCTION <= 0;
end else if ( SIMPLE_MICRO==1 && was_simple == 1) begin
was_simple<=0;
was_dec<=0;
/* verilator lint_off BLKSEQ */
FIFO_start = FIFO_start + {1'b0,Isize};
INSTRUCTION_LOCATION <= INSTRUCTION_LOCATION + {12'b0,Isize};;
/* verilator lint_on BLKSEQ */
VALID_INSTRUCTION <= 0;
end
end
endcase
end
always @( negedge SIMPLE_MICRO ) begin
was_simple <= 1;
end
always @( NEXT_POSITION ) begin
case(NEXT_POSITION)
2'b00:begin end /* no action */
2'b01:begin /* Next instruction */
/* verilator lint_off BLKSEQ */
FIFO_start = FIFO_start + {1'b0,Isize};
INSTRUCTION_LOCATION <= INSTRUCTION_LOCATION + {12'b0,Isize};;
/* verilator lint_on BLKSEQ */
VALID_INSTRUCTION <= 0;
end
2'b10:begin /* Jump to specific location based on register */
jump_req <= 1;

2
system/decoder.v
View File

@ -92,7 +92,7 @@ microcode ucode(seq_addr_input,ucode_data);
// then branching off of that instead of the raw bits. otherwise the code
// would be identical
// verilator lint_off BLKSEQ
always @( CIR or SIMPLE_MICRO or seq_addr_input ) begin
always @( FLAGS or CIR or SIMPLE_MICRO or seq_addr_input ) begin
if (SIMPLE_MICRO==0)begin
casez({CIR[15:8],CIR[5:3]})
11'b0000_010?_??? : begin

15
system/processor.v
View File

@ -49,7 +49,8 @@ wire BIU_VALID_DATA;
BIU BIU(
clock,reset,external_address_bus,external_data_bus,read,write,BHE,IOMEM,
INSTRUCTION,VALID_INSTRUCTION,INSTRUCTION_LOCATION,BIU_NEXT_POSITION,BIU_ADDRESS_INPUT,BIU_DATA,biu_write_request,biu_read_request,Wbit,BIU_VALID_DATA,MEM_OR_IO
INSTRUCTION,VALID_INSTRUCTION,INSTRUCTION_LOCATION,BIU_NEXT_POSITION,BIU_ADDRESS_INPUT,BIU_DATA,biu_write_request,biu_read_request,Wbit,BIU_VALID_DATA,MEM_OR_IO,
state,SIMPLE_MICRO
);
assign BIU_DATA= biu_data_direction ? 16'hz : (memio_address_select?reg_read_port1_data:ALU_1O);
@ -411,7 +412,7 @@ always @(posedge clock) begin
end
end
`PROC_NEXT_INSTRUCTION:begin
BIU_NEXT_POSITION <= 2'b01;
/*necessary for biu to see we went on another state from decode to give us a new instruction*/
state <= `PROC_DE_STATE_ENTRY;
end
`PROC_EX_STATE_ENTRY:begin
@ -460,8 +461,6 @@ always @(posedge clock) begin
state <= `PROC_MEMIO_WRITE;
end
endcase
if(BIU_NEXT_POSITION != 2'b10 )
BIU_NEXT_POSITION <= 2'b01;
end
3'b011:begin
reg_write_we <= 0;
@ -469,16 +468,12 @@ always @(posedge clock) begin
state <= `PROC_DE_STATE_ENTRY;
else
state <= `PROC_NEXT_MICROCODE;
if(BIU_NEXT_POSITION != 2'b10 )
BIU_NEXT_POSITION <= 2'b01;
end
3'b100:begin /*No output*/
if (ucode_seq_addr==`UCODE_NO_INSTRUCTION)
state <= `PROC_DE_STATE_ENTRY;
else
state <= `PROC_NEXT_MICROCODE;
if(BIU_NEXT_POSITION != 2'b10 )
BIU_NEXT_POSITION <= 2'b01;
end
3'b101:begin /* Program Counter*/
BIU_ADDRESS_INPUT <= ALU_1O[15:0];
@ -492,8 +487,6 @@ always @(posedge clock) begin
3'b110:begin /* SP Indirect write*/
reg_read_port1_addr <= 4'b1100;
state <= `PROC_MEMIO_WRITE;
if(BIU_NEXT_POSITION != 2'b10 )
BIU_NEXT_POSITION <= 2'b01;
end
3'b111:begin /* Write to PRAM1 (for microcode calculations) */
PARAM1 <= ALU_1O;
@ -501,8 +494,6 @@ always @(posedge clock) begin
state <= `PROC_DE_STATE_ENTRY;
else
state <= `PROC_NEXT_MICROCODE;
if(BIU_NEXT_POSITION != 2'b10 )
BIU_NEXT_POSITION <= 2'b01;
end
default:begin
`unimpl_addressing_mode