301 lines
9.2 KiB
Verilog
301 lines
9.2 KiB
Verilog
/* processor.v - implementation of most functions of the 9086 processor
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This file is part of the 9086 project.
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Copyright (c) 2023 Efthymios Kritikos
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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`include "exec_state_def.v"
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`include "alu_header.v"
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`include "config.v"
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`include "ucode_header.v"
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`include "error_header.v"
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//HALT: active high
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//IOMEM: 1=IO 0=MEM
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//write: active low
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//read: active low
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//reset: active low
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`define PROC_STATE_BITS 3
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`define PROC_RESET 3'b000
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`define PROC_DE_STATE_ENTRY 3'b001
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`define PROC_WAIT 3'b010
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`define PROC_HALT 3'b011
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module processor ( input clock, input reset, output [19:0] external_address_bus, inout [15:0] external_data_bus,output read, output write,output BHE,output IOMEM, output reg HALT,output [`ERROR_BITS-1:0] ERROR);
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/* If there is an error either from the decoder or execution unit set it to ERROR */
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assign ERROR=(DE_ERROR_sampled!=`ERR_NO_ERROR)?DE_ERROR_sampled:(EXEC_ERROR!=`ERR_NO_ERROR)?EXEC_ERROR:`ERR_NO_ERROR;
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/*** Global Definitions ***/
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reg [`PROC_STATE_BITS-1:0] state;
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/*############ Execution Unit ################################################## */
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reg [1:0] in_alu_sel1;
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reg [1:0] in_alu_sel2;
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wire [`EXEC_STATE_BITS-1:0] exec_state;
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reg valid_exec_data;
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wire [`ERROR_BITS-1:0] EXEC_ERROR;
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wire use_exec_reg_addr;
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wire [3:0] EXEC_reg_read_port1_addr;
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reg [2:0] IN_MOD,OUT_MOD;
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reg [`EXEC_STATE_BITS-1:0] exec_state_init;
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reg [`ALU_OP_BITS-1:0] ALU_OP;
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wire [15:0] ALU_O;
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wire [7:0]EXEC_FLAGS;
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reg [15:0] PARAM1_INIT;
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reg [15:0] PARAM2_INIT;
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reg set_initial_values;
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execute_unit execute_unit (
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/* GENERAL */ clock, reset, Wbit, Sbit, opcode_size, INSTRUCTION_BUFFER,valid_exec_data
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/* */ ,IN_MOD, OUT_MOD,memio_address_select, ProgCount, RM, EXEC_ERROR, write
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/* */ ,set_initial_values
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/* PARAM */ ,PARAM1_INIT,PARAM2_INIT
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/* STATE CONTROL */ ,exec_state, exec_state_init
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/* ALU CONTROL */ ,in_alu_sel1, in_alu_sel2, ALU_OP, ALU_O
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/* REGISTER DATA */ ,reg_read_port1_data, reg_read_port2_data, EXEC_reg_read_port1_addr, use_exec_reg_addr, reg_write_we
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/* FLAFS */ ,EXEC_FLAGS
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/* BIU */ ,BIU_ADDRESS_INPUT, biu_write_request, biu_read_request, BIU_VALID_DATA, BIU_DATA, biu_data_direction, biu_jump_req
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);
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/*############ Bus Interface Unit ############################################### */
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wire [31:0] INSTRUCTION;
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wire biu_jump_req;
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wire VALID_INSTRUCTION;
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wire [15:0] INSTRUCTION_LOCATION;
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wire [15:0] BIU_ADDRESS_INPUT;
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wire [15:0] BIU_DATA;
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wire biu_write_request;
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wire biu_data_direction;
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wire biu_read_request;
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wire BIU_VALID_DATA;
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BIU BIU(
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clock,reset,external_address_bus,external_data_bus,read,write,BHE,IOMEM,
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INSTRUCTION,VALID_INSTRUCTION,INSTRUCTION_LOCATION,biu_jump_req,BIU_ADDRESS_INPUT,BIU_DATA,biu_write_request,biu_read_request,Wbit,BIU_VALID_DATA,MEM_OR_IO,
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state,SIMPLE_MICRO
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);
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assign BIU_DATA= biu_data_direction ? 16'hz : (memio_address_select ? reg_read_port1_data : ALU_O);
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/*############ Decoder ########################################################## */
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reg Wbit, Sbit, opcode_size;
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wire DE_Wbit, DE_Sbit, DE_opcode_size;
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wire [`EXEC_STATE_BITS-1:0] next_state;
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reg [2:0]RM;
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wire [15:0]DE_PARAM1;// Input param1 form decoder to alu
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wire [15:0]DE_PARAM2;
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wire [2:0]DE_IN_MOD;
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wire [2:0]DE_RM;
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wire [2:0]DE_OUT_MOD;
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wire [`ERROR_BITS-1:0] DE_ERROR;
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wire DE_HALT;
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wire [3:0]DE_reg_read_port1_addr,DE_reg_write_addr,DE_reg_read_port2_addr;
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wire [11:0]DE_REGISTER_CONTROL;
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wire [2:0]INSTRUCTION_INFO;
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wire [`ERROR_BITS:0]DECODER_SIGNALS;
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wire [`UCODE_ADDR_BITS-1:0] ucode_seq_addr_entry;
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reg SIMPLE_MICRO; /* output simple decodings (=0) or microcode data (=1) */
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//TODO : remove completely?
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reg memio_address_select;
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wire DE_memio_address_select;
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wire DE_MEM_OR_IO;
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reg MEM_OR_IO;
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wire [1:0] DE_in_alu_sel1;
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wire [1:0] DE_in_alu_sel2;
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reg [`ALU_OP_BITS-1:0] DE_ALU_OP;
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decoder decoder(
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.CIR(INSTRUCTION[31:16]),
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.FLAGS(FLAGS),
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.INSTRUCTION_INFO(INSTRUCTION_INFO),
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.DECODER_SIGNALS(DECODER_SIGNALS),
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.next_state(next_state),
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.IN_MOD(DE_IN_MOD),
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.RM(DE_RM),
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.PARAM1(DE_PARAM1),
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.PARAM2(DE_PARAM2),
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.in_alu_sel1(DE_in_alu_sel1),
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.in_alu_sel2(DE_in_alu_sel2),
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.OUT_MOD(DE_OUT_MOD),
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.REGISTER_FILE_CONTROL(DE_REGISTER_CONTROL),
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.ALU_1OP(DE_ALU_OP),
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.seq_addr_entry(ucode_seq_addr_entry),
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.SIMPLE_MICRO(SIMPLE_MICRO),
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.seq_addr_input(ucode_seq_addr),
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.memio_address_select(DE_memio_address_select),
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.MEM_OR_IO(DE_MEM_OR_IO)
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);
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assign DE_Wbit=INSTRUCTION_INFO[2:2];
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assign DE_Sbit=INSTRUCTION_INFO[1:1];
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assign DE_opcode_size=INSTRUCTION_INFO[0:0];
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assign DE_reg_write_addr=DE_REGISTER_CONTROL[11:8];
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assign DE_reg_read_port1_addr=DE_REGISTER_CONTROL[7:4];
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assign DE_reg_read_port2_addr=DE_REGISTER_CONTROL[3:0];
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assign DE_HALT=DECODER_SIGNALS[0:0];
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assign DE_ERROR=DECODER_SIGNALS[`ERROR_BITS:1];
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reg [`ERROR_BITS-1:0] DE_ERROR_sampled;
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reg [`UCODE_ADDR_BITS-1:0] ucode_seq_addr;
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/*############ REGISTERS ########################################################## */
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// verilator lint_off UNDRIVEN
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reg [15:0] FLAGS;
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// verilator lint_on UNDRIVEN
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//Architectural Register file
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reg [3:0] reg_write_addr;
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wire [15:0] reg_write_data;
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wire reg_write_we;
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wire [3:0] reg_read_port1_addr;
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reg [15:0] reg_read_port1_data;
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reg [3:0] reg_read_port2_addr;
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reg [15:0] reg_read_port2_data;
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reg [1:0] reg_write_in_sel;
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mux4 #(.WIDTH(16)) REG_FILE_WRITE_IN_MUX(
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ALU_O,
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16'hz,
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16'hz,
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16'hz,
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reg_write_in_sel,
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reg_write_data);
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register_file register_file(
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.write_port1_addr(reg_write_addr),
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.write_port1_data(reg_write_data),
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.write_port1_we(reg_write_we),
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.read_port1_addr(reg_read_port1_addr),
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.read_port1_data(reg_read_port1_data),
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.read_port2_addr(reg_read_port2_addr),
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.read_port2_data(reg_read_port2_data)
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);
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assign reg_read_port1_addr = use_exec_reg_addr ? EXEC_reg_read_port1_addr : reg_read_port1_addr_latched;
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reg [15:0] ProgCount;
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/*############ Processor state machine ########################################################## */
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reg [3:0] reg_read_port1_addr_latched;
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/*** RESET LOGIC ***/
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/* verilator lint_off MULTIDRIVEN */
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always @(negedge reset) begin
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state <= `PROC_HALT; //TODO: race condition ??
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end
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always @(posedge reset) begin
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state <= `PROC_RESET;
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end
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/* verilator lint_on MULTIDRIVEN */
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/*** Processor stages ***/
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wire [2:0] instr_end;
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InstrSize InstrSize({INSTRUCTION[31:24],INSTRUCTION[21:19]},instr_end);
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reg [23:0] INSTRUCTION_BUFFER;
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always @(posedge clock) begin
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case(state)
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`PROC_RESET:begin
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ucode_seq_addr <= `UCODE_NO_INSTRUCTION;
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HALT <= 0;
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SIMPLE_MICRO <= 0;
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state <= `PROC_DE_STATE_ENTRY;
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reg_write_in_sel <= 2'b00; //only got wirtten in IF
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end
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`PROC_DE_STATE_ENTRY:begin
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if(VALID_INSTRUCTION==1) begin
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if(SIMPLE_MICRO==0)begin
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/* We cannot set these directly within
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* microcode so don't overwrite useful values
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* each tie the next microcode is executed.
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* Note this still allows to set initial values
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* at the start of the microcode */
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PARAM1_INIT <= DE_PARAM1;
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PARAM2_INIT <= DE_PARAM2;
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`ifdef DEBUG_PC_ADDRESS
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$display("Running command at %04x (%08x)",INSTRUCTION_LOCATION,INSTRUCTION);
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`endif
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ProgCount <= INSTRUCTION_LOCATION+{12'b0,instr_end};
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INSTRUCTION_BUFFER<=INSTRUCTION[23:0];
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set_initial_values<=0;
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end
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DE_ERROR_sampled <= DE_ERROR;
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IN_MOD <= DE_IN_MOD;
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OUT_MOD <= DE_OUT_MOD;
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RM <= DE_RM;
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HALT <= DE_HALT;
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Wbit <= DE_Wbit;
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Sbit <= DE_Sbit;
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opcode_size <= DE_opcode_size;
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memio_address_select<=DE_memio_address_select;
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reg_read_port1_addr_latched <= DE_reg_read_port1_addr;
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reg_read_port2_addr <= DE_reg_read_port2_addr;
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reg_write_addr <= DE_reg_write_addr;
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MEM_OR_IO <= DE_MEM_OR_IO;
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in_alu_sel1 <= DE_in_alu_sel1;
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in_alu_sel2 <= DE_in_alu_sel2;
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ALU_OP <= DE_ALU_OP;
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if ( (ucode_seq_addr==`UCODE_NO_INSTRUCTION) && (ucode_seq_addr_entry!=`UCODE_NO_INSTRUCTION) )begin
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/*switch to microcode decoding*/
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ucode_seq_addr <= ucode_seq_addr_entry;
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SIMPLE_MICRO <= 1;
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/*keep state the same and rerun decode this time with all the data from the microcode rom*/
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end else begin
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valid_exec_data <= 1;
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exec_state_init <= next_state;
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state <= `PROC_WAIT;
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end
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end
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end
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`PROC_WAIT:begin
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set_initial_values<=1;
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if( exec_state == `EXEC_DONE ) begin
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FLAGS[7:0] <= EXEC_FLAGS; //don't set all of them all the time!
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valid_exec_data<=0;
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state <= `PROC_DE_STATE_ENTRY;
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if(SIMPLE_MICRO == 1 ) begin
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ucode_seq_addr <= ucode_seq_addr_entry; /*Reused for next address*/
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if( ucode_seq_addr_entry == `UCODE_NO_INSTRUCTION )begin
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/*Finished microcode*/
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SIMPLE_MICRO <= 0;
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end
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end
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end
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end
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`PROC_HALT:begin
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end
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default:begin
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end
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endcase
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end
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endmodule
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