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9086/system/processor.v

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/* processor.v - implementation of most functions of the 9086 processor
This file is part of the 9086 project.
Copyright (c) 2023 Efthymios Kritikos
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
`include "proc_state_def.v"
`include "alu_header.v"
`include "config.v"
`include "ucode_header.v"
module processor ( input clock, input reset, output reg [19:0] external_address_bus, inout [15:0] external_data_bus,output reg read, output reg write, output reg HALT,output reg ERROR);
/*if we don't read, output the register to have the bus stable by the write falling edge*/
reg [15:0] data_bus_output_register;
assign external_data_bus=read?data_bus_output_register:16'hz;
/*** Global Definitions ***/
reg [`PROC_STATE_BITS-1:0] state;
/*############ Decoder ########################################################## */
wire Wbit, Sbit, unaligning_instruction,opcode_size, has_operands;
wire [`PROC_STATE_BITS-1:0] next_state;
wire [2:0]RM;
wire [15:0]DE_PARAM1;// Input param1 form decoder to alu
wire [15:0]DE_PARAM2;
wire DE_ERROR,DE_HALT;
wire [3:0]DE_reg_read_port1_addr,DE_reg_write_addr,DE_reg_read_port2_addr;
wire [11:0]DE_REGISTER_CONTROL;
wire [4:0]INSTRUCTION_INFO;
wire [1:0]DECODER_SIGNALS;
wire [`UCODE_ADDR_BITS-1:0] ucode_seq_addr_entry;
reg SIMPLE_MICRO; /* otuput simple decodings (=0) or microcode data (=1) */
decoder decoder(
CIR,FLAGS,INSTRUCTION_INFO,DECODER_SIGNALS,next_state
,IN_MOD,RM,DE_PARAM1,DE_PARAM2
,in_alu1_sel1,in_alu1_sel2,OUT_MOD
,DE_REGISTER_CONTROL
,ALU_1OP
,ucode_seq_addr_entry,SIMPLE_MICRO,ucode_seq_addr
);
assign Wbit=INSTRUCTION_INFO[4:4];
assign Sbit=INSTRUCTION_INFO[3:3];
assign unaligning_instruction=INSTRUCTION_INFO[2:2];
assign opcode_size=INSTRUCTION_INFO[1:1];
assign has_operands=INSTRUCTION_INFO[0:0];
assign DE_reg_write_addr=DE_REGISTER_CONTROL[11:8];
assign DE_reg_read_port1_addr=DE_REGISTER_CONTROL[7:4];
assign DE_reg_read_port2_addr=DE_REGISTER_CONTROL[3:0];
assign DE_HALT=DECODER_SIGNALS[0:0];
assign DE_ERROR=DECODER_SIGNALS[1:1];
reg [`UCODE_ADDR_BITS-1:0] ucode_seq_addr;
/*############ REGISTERS ########################################################## */
reg [19:0] ProgCount; //TODO: do i create a lot of adders each place i increment it?
reg [15:0] CIR;
reg [15:0] PARAM1;
reg [15:0] PARAM2;
reg one_byte_instruction;
reg unaligned_access;
reg we_jumped; /*Only used to signify that a microcoded instruction jumped and we should not update the unaligned_access bit after the end of the instruction*/
reg [15:0]FLAGS;
reg [15:0] BYTE_WRITE_TEMP_REG;//we read 16bits here if we want to change just 8 and leave the rest
//Architectural Register file
reg [3:0] reg_write_addr;
wire [15:0] reg_write_data;
reg reg_write_we;
reg [3:0] reg_read_port1_addr;
reg [15:0] reg_read_port1_data;
reg [3:0] reg_read_port2_addr;
reg [15:0] reg_read_port2_data;
reg [1:0] reg_write_in_sel;
mux4 #(.WIDTH(16)) REG_FILE_WRITE_IN_MUX(
ALU_1O,
16'hz,
16'hz,
16'hz,
reg_write_in_sel,
reg_write_data);
register_file register_file(reg_write_addr,reg_write_data,reg_write_we,reg_read_port1_addr,reg_read_port1_data,reg_read_port2_addr,reg_read_port2_data);
/*############ ALU / Execution units ########################################################## */
// ALU 1
reg [1:0] in_alu1_sel1;
reg [1:0] in_alu1_sel2;
/* OUT_MOD : { EXTRA_FUNCTIONS_BIT[0:0], MOD_OR_EXTRA_FUNCTION[1:0] } */
reg [2:0] IN_MOD;
reg [2:0] OUT_MOD;
mux4 #(.WIDTH(16)) MUX16_1A(
PARAM1,
reg_read_port1_data,
{ProgCount[14:0],unaligned_access^unaligning_instruction},
16'b0000000000000000, /*0 Constant*/
in_alu1_sel1,
ALU_1A);
mux4 #(.WIDTH(16)) MUX16_1B(
PARAM2,
reg_read_port2_data,
{ProgCount[14:0],unaligned_access^unaligning_instruction},
16'b0000000000000000, /*0 Constant*/
in_alu1_sel2,
ALU_1B);
wire [15:0] ALU_1A;
wire [15:0] ALU_1B;
wire [15:0] ALU_1O;
reg [`ALU_OP_BITS-1:0]ALU_1OP;
wire [7:0] ALU_1FLAGS;
ALU ALU1(ALU_1A,ALU_1B,ALU_1O,ALU_1OP,ALU_1FLAGS,Wbit);
/*############ Processor state machine ########################################################## */
/*** RESET LOGIC ***/
always @(negedge reset) begin
if (reset==0) begin
@(posedge clock);
state=`PROC_HALT_STATE;
ucode_seq_addr=`UCODE_NO_INSTRUCTION;
ProgCount=0;//TODO: Reset Vector
HALT=0;
reg_write_we=1;
unaligned_access=0;
@(posedge reset)
@(negedge clock);
state=`PROC_IF_STATE_ENTRY;
one_byte_instruction=0;
ERROR=0;
SIMPLE_MICRO=0;
end
end
/*** Processor stages ***/
`define invalid_instruction state=`PROC_IF_STATE_ENTRY;ERROR=1;
always @(negedge clock) begin
case(state)
`PROC_IF_WRITE_CIR:begin
if(unaligned_access)begin
if(one_byte_instruction==1)begin /*TODO: have a read buffer so we can do this even with data reads */
CIR <= {CIR[7:0],external_data_bus[15:8]};
state=`PROC_DE_STATE_ENTRY;
end else begin
CIR[15:8] <= external_data_bus[7:0];
state=`PROC_IF_STATE_EXTRA_FETCH_SET;
end
end else begin
CIR <= external_data_bus;
ProgCount=ProgCount+1;
state=`PROC_DE_STATE_ENTRY;
end
end
`PROC_IF_STATE_EXTRA_FETCH:begin
CIR[7:0] <= external_data_bus[15:8];
state=`PROC_DE_STATE_ENTRY;
end
`PROC_EX_STATE_EXIT:begin
/*Don't update the unaligned_access for Instruction
* Fetch if we are doing microcode execution, it will
* be done by decode at the end*/
if (ucode_seq_addr==`UCODE_NO_INSTRUCTION)
unaligned_access=unaligning_instruction^unaligned_access;
case(OUT_MOD) /*TODO: use RM*/
3'b000,
3'b001,
3'b010 : begin
case (RM) /* Duplicate code with write... */
3'b000:begin
/*[BX]+[SI]*/
`invalid_instruction
end
3'b001:begin
/*[BX]+[SI]*/
`invalid_instruction
end
3'b010:begin
/*[BP]+[SI]*/
`invalid_instruction
end
3'b011:begin
/*[BP]+[DI]*/
`invalid_instruction
end
3'b100:begin
/*[SI]*/
reg_read_port1_addr=4'b1110;
state=`PROC_MEMIO_WRITE;
end
3'b101:begin
/*[DI]*/
reg_read_port1_addr=4'b1111;
state=`PROC_MEMIO_WRITE;
end
3'b110:begin
/*d16 */
`invalid_instruction
end
3'b111:begin
/*[BX]*/
reg_read_port1_addr=4'b1011;
state=`PROC_MEMIO_WRITE;
end
endcase
end
3'b011:begin
reg_write_we=0;
if (ucode_seq_addr==`UCODE_NO_INSTRUCTION)
state=`PROC_IF_STATE_ENTRY;
else
state=`PROC_NEXT_MICROCODE;
end
3'b100:begin /*No output*/
if (ucode_seq_addr==`UCODE_NO_INSTRUCTION)
state=`PROC_IF_STATE_ENTRY;
else
state=`PROC_NEXT_MICROCODE;
end
3'b101:begin /* Program Counter*/
ProgCount={5'b00000,ALU_1O[15:1]};
unaligned_access=ALU_1O[0:0];
we_jumped=1;
if (ucode_seq_addr==`UCODE_NO_INSTRUCTION)
state=`PROC_IF_STATE_ENTRY;
else
state=`PROC_NEXT_MICROCODE;
end
3'b110:begin /* SP Indirect write*/
reg_read_port1_addr=4'b1100;
state=`PROC_MEMIO_WRITE;
end
default:begin
`invalid_instruction
end
endcase
end
`PROC_DE_LOAD_16_EXTRA_FETCH_SET:begin
external_address_bus = ProgCount;
state=`PROC_DE_LOAD_16_EXTRA_FETCH;
end
`PROC_MEMIO_READ_SETADDR:begin
external_address_bus = {5'b00000,reg_read_port1_data[15:1]};
state=reg_read_port1_data[0:0]?`PROC_MEMIO_GET_UNALIGNED_DATA:`PROC_MEMIO_GET_ALIGNED_DATA;
end
`PROC_MEMIO_PUT_BYTE:begin
BYTE_WRITE_TEMP_REG=external_data_bus;
state=`PROC_MEMIO_PUT_BYTE_STOP_READ;
end
`PROC_MEMIO_WRITE_EXIT:begin
write=0;
if (ucode_seq_addr==`UCODE_NO_INSTRUCTION)
state=`PROC_IF_STATE_ENTRY;
else
state=`PROC_NEXT_MICROCODE;
end
`PROC_MEMIO_PUT_ALIGNED_DATA:begin
read=1;
data_bus_output_register={ALU_1O[7:0],ALU_1O[15:8]};
state=`PROC_MEMIO_WRITE_EXIT;
end
`PROC_MEMIO_PUT_UNALIGNED_DATA:begin
BYTE_WRITE_TEMP_REG=external_data_bus;
state=`PROC_MEMIO_PUT_UNALIGNED_FIRST_BYTE;
end
`PROC_MEMIO_PUT_UNALIGNED_PREP_NEXT:begin
write=0;
state=`PROC_MEMIO_PUT_UNALIGNED_PREP_NEXT2;
data_bus_output_register={BYTE_WRITE_TEMP_REG[15:8],ALU_1O[7:0]};
end
`PROC_MEMIO_PUT_UNALIGNED_PREP_NEXT3:begin
BYTE_WRITE_TEMP_REG=external_data_bus;
state=`PROC_MEMIO_PUT_UNALIGNED_PREP_NEXT4;
end
`PROC_MEMIO_GET_SECOND_BYTE:begin
external_address_bus=external_address_bus+1;
state=`PROC_MEMIO_GET_SECOND_BYTE1;
end
`PROC_DE_LOAD_8_PARAM_UNALIGNED:begin
if({Sbit,Wbit}==2'b11)begin
PARAM1 = {{8{external_data_bus[15:15]}},external_data_bus[15:8]};
end else begin
PARAM1[7:0] = external_data_bus[15:8];
end
state=`PROC_EX_STATE_ENTRY;
end
default:begin
end
endcase
end
always @(posedge clock) begin
case(state)
`PROC_HALT_STATE:begin
end
`PROC_IF_STATE_ENTRY:begin
`ifdef DEBUG_PC_ADDRESS
/* Weird (possible bug) where even though the
* testbench stop the clock after ERROR gets
* raised the logic for the rising edge still
* gets triggered printing this debug message. */
if(ERROR!=1)
$display("Fetched instruction at %04x",{ProgCount[18:0],unaligned_access});
`endif
external_address_bus = ProgCount;
read = 0;
write = 1;
reg_write_we=1;
state=`PROC_IF_WRITE_CIR;
reg_write_in_sel=2'b00;
we_jumped=0;
end
`PROC_IF_STATE_EXTRA_FETCH_SET:begin
ProgCount=ProgCount+1;
external_address_bus = ProgCount;
state=`PROC_IF_STATE_EXTRA_FETCH;
end
`PROC_DE_STATE_ENTRY:begin
/* If we are unaligned, the address bus contains the
* ProgCount and points to the second word containing
* the nest unread byte in extenral_data_bus[7:0]. If
* we are aligned the address bus points to the first
* word of the instruction which contains no useful
* data anymore but the ProgCount has the correct
* address so update it now so that whatever the case
* external_data_bus contains at least some unknown data */
one_byte_instruction=(!has_operands)&&(!opcode_size);
external_address_bus = ProgCount;
if(SIMPLE_MICRO==0)begin
/* We cannot set these directly within
* microcode so don't overwirte useful values
* each time the next microcode is executed.
* Note this still allows to set initial values
* at the start of the microcode */
PARAM1=DE_PARAM1;
PARAM2=DE_PARAM2;
end
ERROR=DE_ERROR;
HALT=DE_HALT;
reg_read_port1_addr=DE_reg_read_port1_addr;
reg_read_port2_addr=DE_reg_read_port2_addr;
reg_write_addr=DE_reg_write_addr;
if ( (ucode_seq_addr==`UCODE_NO_INSTRUCTION) && (ucode_seq_addr_entry!=`UCODE_NO_INSTRUCTION) )begin
/*switch to microcode decoding*/
ucode_seq_addr=ucode_seq_addr_entry;
SIMPLE_MICRO=1;
/*keep state the same and rerun decode this time with all the data from the microcode rom*/
end else begin
state=next_state;
end
end
`PROC_DE_LOAD_REG_TO_PARAM:begin
PARAM2=reg_read_port2_data;
state=`PROC_EX_STATE_ENTRY;
end
`PROC_DE_LOAD_8_PARAM:begin
if(opcode_size==0)begin
if({Sbit,Wbit}==2'b11)begin
/*signed "16bit" read*/
PARAM1 = {{8{CIR[7:7]}},CIR[7:0]};
end else begin
PARAM1[7:0] = CIR[7:0];
end
state=`PROC_EX_STATE_ENTRY;
end else begin
if(unaligned_access==1)begin
if({Sbit,Wbit}==2'b11)begin
/*signed "16bit" read*/
PARAM1 = {{8{external_data_bus[7:7]}},external_data_bus[7:0]};
end else begin
PARAM1[7:0] = external_data_bus[7:0];
end
ProgCount=ProgCount+1;
state=`PROC_EX_STATE_ENTRY;
end else begin
external_address_bus=ProgCount;
state=`PROC_DE_LOAD_8_PARAM_UNALIGNED;
end
end
end
`PROC_DE_LOAD_16_PARAM:begin
if(opcode_size==0)begin
if(unaligned_access==1)begin
PARAM1 = {external_data_bus[7:0],external_data_bus[15:8]};
ProgCount=ProgCount+1;
end else begin
PARAM1 = {external_data_bus[15:8],CIR[7:0]};
end
case(IN_MOD)
3'b000,3'b001,3'b010: state=`PROC_MEMIO_READ;
default: state=`PROC_EX_STATE_ENTRY;
endcase
end else begin
ProgCount=ProgCount+1;
if(unaligned_access==1)begin
PARAM1[7:0] = external_data_bus[7:0];
state=`PROC_DE_LOAD_16_EXTRA_FETCH_SET;
end else begin
PARAM1 = {external_data_bus[7:0],external_data_bus[15:8]};
case(IN_MOD)
3'b000,3'b001,3'b010: state=`PROC_MEMIO_READ;
default: state=`PROC_EX_STATE_ENTRY;
endcase
end
end
end
`PROC_DE_LOAD_16_EXTRA_FETCH:begin
PARAM1[15:8] = external_data_bus[15:8];
case(IN_MOD)
3'b000,3'b001,3'b010: state=`PROC_MEMIO_READ;
default: state=`PROC_EX_STATE_ENTRY;
endcase
end
`PROC_MEMIO_READ:begin
/*Decode MOD R/M, read the data and place it to PARAM1*/
case (IN_MOD)
3'b000,
3'b001,
3'b010:begin
case (RM)
3'b000:begin
/*[BX]+[SI]*/
`invalid_instruction
end
3'b001:begin
/*[BX]+[SI]*/
`invalid_instruction
end
3'b010:begin
/*[BP]+[SI]*/
`invalid_instruction
end
3'b011:begin
/*[BP]+[DI]*/
`invalid_instruction
end
3'b100:begin
/*[SI]*/
reg_read_port1_addr=4'b1110;
state=`PROC_MEMIO_READ_SETADDR;
end
3'b101:begin
/*[DI]*/
reg_read_port1_addr=4'b1111;
state=`PROC_MEMIO_READ_SETADDR;
end
3'b110:begin
/*d16 */
`invalid_instruction
end
3'b111:begin
/*[BX]*/
reg_read_port1_addr=4'b1011;
state=`PROC_MEMIO_READ_SETADDR;
end
endcase
if(IN_MOD!=3'b000)begin
/*Actually check if 01 and add the 8bits or if 10 add the 16bits ....*/
`invalid_instruction;
end
end
3'b110:begin /* SP Indirect read*/
reg_read_port1_addr=4'b1100;
state=`PROC_MEMIO_READ_SETADDR;
end
default:begin
`invalid_instruction
end
endcase
end
`PROC_MEMIO_GET_ALIGNED_DATA:begin
PARAM2=(Wbit==1)? {external_data_bus[7:0],external_data_bus[15:8]} : {8'b00000000,external_data_bus[15:8]} ;
state=`PROC_EX_STATE_ENTRY;
end
`PROC_MEMIO_GET_UNALIGNED_DATA:begin
PARAM2={8'b00000000,external_data_bus[7:0]};
if(Wbit==1) begin
state=`PROC_MEMIO_GET_SECOND_BYTE;
end else begin
state=`PROC_EX_STATE_ENTRY;
end
end
`PROC_EX_STATE_ENTRY:begin
FLAGS[7:0] = ALU_1FLAGS[7:0];
state=`PROC_EX_STATE_EXIT;
end
`PROC_MEMIO_WRITE:begin
/* ADDRESS: reg_read_port1_data DATA:ALU1_O */
`ifdef DEBUG_MEMORY_WRITES
$display("Writing at %04x , %04x",reg_read_port1_data,ALU_1O);
`endif
external_address_bus = {5'b00000,reg_read_port1_data[15:1]};
state = (Wbit==0) ? `PROC_MEMIO_PUT_BYTE : (reg_read_port1_data[0:0]?`PROC_MEMIO_PUT_UNALIGNED_DATA:`PROC_MEMIO_PUT_ALIGNED_DATA) ;
end
`PROC_MEMIO_PUT_BYTE_STOP_READ:begin
read=1;
state=`PROC_MEMIO_WRITE_EXIT;
if(reg_read_port1_data[0:0]==0)
data_bus_output_register={ALU_1O[7:0],BYTE_WRITE_TEMP_REG[7:0]};
else
data_bus_output_register={BYTE_WRITE_TEMP_REG[15:8],ALU_1O[7:0]};
end
`PROC_MEMIO_PUT_UNALIGNED_FIRST_BYTE:begin
read=1;
state=`PROC_MEMIO_PUT_UNALIGNED_PREP_NEXT;
data_bus_output_register={BYTE_WRITE_TEMP_REG[15:8],ALU_1O[7:0]};
end
`PROC_MEMIO_PUT_UNALIGNED_PREP_NEXT2:begin
external_address_bus=external_address_bus+1;
write=1;
read=0;
state=`PROC_MEMIO_PUT_UNALIGNED_PREP_NEXT3;
end
`PROC_MEMIO_PUT_UNALIGNED_PREP_NEXT4:begin
read=1;
state=`PROC_MEMIO_WRITE_EXIT;
data_bus_output_register={ALU_1O[15:8],BYTE_WRITE_TEMP_REG[7:0]};
end
`PROC_MEMIO_GET_SECOND_BYTE1:begin
PARAM2[15:8]=external_data_bus[15:8];
state=`PROC_EX_STATE_ENTRY;
end
`PROC_NEXT_MICROCODE:begin
read=0;
write=1; // maybe we are coming from MEMIO_WRITE
ucode_seq_addr=ucode_seq_addr_entry; /*Reused for next address*/
if( ucode_seq_addr == `UCODE_NO_INSTRUCTION )begin
/*Finished microcode*/
if(we_jumped==0)
unaligned_access=unaligning_instruction^unaligned_access;
SIMPLE_MICRO=0;
state=`PROC_IF_STATE_ENTRY;
end else begin
state=`PROC_DE_STATE_ENTRY;
end
end
default:begin
end
endcase
end
endmodule
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