Boot_code/BIOS: Split the litedram init off to a separate file and included the brainfuck compiler in the bios as a demo for the ram. Also added code to zero out the brainfuck data in the compiler
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286
boot_code/LiteDram_init.asm
Normal file
286
boot_code/LiteDram_init.asm
Normal file
@ -0,0 +1,286 @@
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litedram_init:
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mov bx,#initdram_txt
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call print
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WAIT_PLL:
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inw #0x20
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test al,#0x04
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jz WAIT_PLL
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;;; DO ALL INIT STUFF ;;;
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;////sdram_software_control_on///
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MOV BX,#0x0000
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MOV AX,#0x000E
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call sdram_dfii_control_write
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;/////////////////////////////////
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MOV BX,#0x0000
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MOV AX,#0x0000
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CALL ddrctrl_init_done_write
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mov bx,#0x0000
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mov ax,#0x0000
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call ddrctrl_init_error_write
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mov bx,#0x0000
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mov ax,#0x000C
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call sdram_dfii_control_write
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MOV DL,#0xF0
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DELAY11:
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MOV AX,#0xF000
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DELAY1:
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INC AX
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JNZ DELAY1
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INC DL
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JNZ DELAY11
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MOV BX,#0x0000
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MOV AX,#0x0000
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call sdram_dfii_pi0_address_write
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mov bx,#0x0000
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mov ax,#0x0000
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call sdram_dfii_pi0_baddress_write
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mov bx,#0x0000
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mov ax,#0x000E
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call sdram_dfii_control_write
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MOV DL,#0xF0
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DELAY21:
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MOV AX,#0xF000
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DELAY2:
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INC AX
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JNZ DELAY2
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INC DL
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JNZ DELAY21
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MOV BX,#0x0000
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MOV AX,#0x0200
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call sdram_dfii_pi0_address_write
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mov bx,#0x0000
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mov ax,#0x0002
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call sdram_dfii_pi0_baddress_write
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mov bx,#0x0000
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mov ax,#0x000F
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call command_p0
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MOV BX,#0x0000
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MOV AX,#0x0000
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call sdram_dfii_pi0_address_write
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mov bx,#0x0000
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mov ax,#0x0003
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call sdram_dfii_pi0_baddress_write
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mov bx,#0x0000
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mov ax,#0x000F
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call command_p0
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MOV BX,#0x0000
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MOV AX,#0x0006
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call sdram_dfii_pi0_address_write
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mov bx,#0x0000
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mov ax,#0x0001
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call sdram_dfii_pi0_baddress_write
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mov bx,#0x0000
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mov ax,#0x000F
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call command_p0
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MOV BX,#0x0000
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MOV AX,#0x0320
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call sdram_dfii_pi0_address_write
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mov bx,#0x0000
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mov ax,#0x0000
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call sdram_dfii_pi0_baddress_write
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mov bx,#0x0000
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mov ax,#0x000F
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call command_p0
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MOV DL,#0xF0
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DELAY31:
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MOV AX,#0xF000
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DELAY3:
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INC AX
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JNZ DELAY3
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INC DL
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JNZ DELAY31
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MOV BX,#0x0000
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MOV AX,#0x0400
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call sdram_dfii_pi0_address_write
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mov bx,#0x0000
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mov ax,#0x0000
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call sdram_dfii_pi0_baddress_write
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mov bx,#0x0000
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mov ax,#0x0003
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call command_p0
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;////sdram_software_control_off///
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MOV BX,#0x0000
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MOV AX,#0x0001
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call sdram_dfii_control_write
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;////////////////////////////////
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;Signify end of init
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MOV BX,#0x0000
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MOV AX,#0x0001
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CALL ddrctrl_init_done_write
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;;;;;;;;;; PROBABLY NOT NECESSARY
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MOV DL,#0xF0
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DELAY41:
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MOV AX,#0xF000
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DELAY4:
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INC AX
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JNZ DELAY4
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INC DL
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JNZ DELAY41
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;;; CHECK ;;;
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inw #0x20
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test al,#0x01
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jz failram
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mov bx,#OK_txt
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call print
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JMP FINISHED_DDR
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failram:
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mov bx,#FAIL_txt
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call print
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mov bx,#NOT_RDY_txt
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call print
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inw #0x20
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test al,#0x02
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jz skip_err
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mov bx,#ERR_ASRT_txt
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call print
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skip_err:
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inw #0x20
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test al,#0x04
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jnz skip_pll
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mov bx,#PLL_ERR_txt
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call print
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skip_pll:
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hlt
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FINISHED_DDR:
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MOV DI,#0x0700
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MOV AX,#0xAAAA
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MOV [DI],AX
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MOV AX,#0x6666
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MOV AX,[DI]
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CMP AX,#0xAAAA
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JNZ FAILED
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MOV BX,#MEMTEST_PASS
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CALL print
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RET
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FAILED:
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MOV BX,#MEMTEST_FAIL
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CALL print
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HLT
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;;; HELPER FUNCTION
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command_p0:
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call WISHBONE_SET_DATA
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MOV AX,#0x0401 ;ORIG=0x1804L
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CALL WISHBONE_SET_ADDRESS
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CALL DO_WRITE_TRANSACTION
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MOV AX,#0x0001
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MOV BX,#0x0000
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call WISHBONE_SET_DATA
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MOV AX,#0x0402 ;ORIG=0x1808L
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CALL WISHBONE_SET_ADDRESS
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CALL DO_WRITE_TRANSACTION
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ret
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#AX: Lower 16 bits data
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#BX: Upper 16 bits data
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sdram_dfii_pi0_address_write:
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call WISHBONE_SET_DATA
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MOV AX,#0x0403 ;ORIG=0x180cL
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CALL WISHBONE_SET_ADDRESS
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CALL DO_WRITE_TRANSACTION
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ret
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sdram_dfii_pi0_baddress_write:
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call WISHBONE_SET_DATA
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MOV AX,#0x0404 ;ORIG=0x1810L
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CALL WISHBONE_SET_ADDRESS
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CALL DO_WRITE_TRANSACTION
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ret
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sdram_dfii_control_write:
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call WISHBONE_SET_DATA
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MOV AX,#0x0400 ;ORIG=0x1800L
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CALL WISHBONE_SET_ADDRESS
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CALL DO_WRITE_TRANSACTION
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ret
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ddrctrl_init_done_write:
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call WISHBONE_SET_DATA
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MOV AX,#0x0000 ;ORIG=0x0L
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CALL WISHBONE_SET_ADDRESS
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CALL DO_WRITE_TRANSACTION
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ret
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ddrctrl_init_error_write:
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call WISHBONE_SET_DATA
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MOV AX,#0x0001 ;ORIG=0x4L
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CALL WISHBONE_SET_ADDRESS
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CALL DO_WRITE_TRANSACTION
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ret
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;
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DO_WRITE_TRANSACTION:
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mov ax,#0x01
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outw #0x46
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mov bl,#0x01
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WB_WRITE_LOOP:
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inc bl
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jz WB_WRITE_TIMEOUT
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inw #0x44
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test al,#0x01
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jz WB_WRITE_LOOP
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test al,#0x04
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jnz WB_WRITE_ERR
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ret
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WB_WRITE_TIMEOUT:
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mov bx,#WISHBONE_TIMEOUT_txt
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call print
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hlt
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WB_WRITE_ERR:
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mov bx,#WISHBONE_ERROR_txt
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call print
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hlt
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#AX: address
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WISHBONE_SET_ADDRESS:
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outw #0x44
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ret
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#AX: Lower 16bits
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#BX: Upper 16bits
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WISHBONE_SET_DATA:
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outw #0x40
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MOV AX,BX
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outw #0x42
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ret
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initdram_txt: .ASCII 'Init LiteDram: \0'
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OK_txt: .ASCII 'OK\n\0'
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PLL_ERR_txt: .ASCII 'PLL_ERR \0' ; PLL_ERR: pll_lock is not asserted
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ERR_ASRT_txt: .ASCII 'ERR_ASRT \0' ; ERR_ASRT: init_error is asserted
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NOT_RDY_txt: .ASCII 'NOT_RDY \0' ; NOT READY: init_done is not asserted
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FAIL_txt: .ASCII 'FAIL\n\0'
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WISHBONE_TIMEOUT_txt: .ASCII 'FAIL\nWISHBONE TIMEOUT\0'
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WISHBONE_ERROR_txt: .ASCII 'FAIL\nWISHBONE ERROR\0'
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MEMTEST_PASS: .ASCII 'MEMTEST PASSED\n\0'
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MEMTEST_FAIL: .ASCII 'MEMTEST FAILED\n\0'
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@ -12,6 +12,7 @@ brainfuck_interpreted.bin: brainfuck_interpreter_v0.asm hello_9086.bf.asm dos_la
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brainfuck_compiled.bin: brainfuck_compiler_v1.asm hello_9086.bf.asm dos_layer.asm
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brainfuck_mandelbrot.bin: brainfuck_compiler_v1.asm mandelbrot.bf.asm dos_layer.asm
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colored_led.bin: dos_layer.asm
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bios.bin: LiteDram_init.asm brainfuck_compiler_v1.asm
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fibonacci.bin: helpers.asm
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gnome_sort.bin: helpers.asm
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@ -1,367 +1,13 @@
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.org 0xF800
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mov sp,#STACK
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mov bx,#initdram_txt
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call print
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call litedram_init
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call INIT_INT_VECT_TABLE
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INCLUDE brainfuck_compiler_v1.asm
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prog:
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INCLUDE hello_9086.bf.asm
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WAIT_PLL:
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inw #0x20
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test al,#0x04
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jz WAIT_PLL
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;;; DO ALL INIT STUFF ;;;
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;////sdram_software_control_on///
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MOV BX,#0x0000
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MOV AX,#0x000E
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call sdram_dfii_control_write
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;/////////////////////////////////
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MOV BX,#0x0000
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MOV AX,#0x0000
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CALL ddrctrl_init_done_write
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mov bx,#0x0000
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mov ax,#0x0000
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call ddrctrl_init_error_write
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mov bx,#0x0000
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mov ax,#0x000C
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call sdram_dfii_control_write
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MOV DL,#0xF0
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DELAY11:
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MOV AX,#0xF000
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DELAY1:
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INC AX
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JNZ DELAY1
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INC DL
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JNZ DELAY11
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MOV BX,#0x0000
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MOV AX,#0x0000
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call sdram_dfii_pi0_address_write
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mov bx,#0x0000
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mov ax,#0x0000
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call sdram_dfii_pi0_baddress_write
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mov bx,#0x0000
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mov ax,#0x000E
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call sdram_dfii_control_write
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MOV DL,#0xF0
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DELAY21:
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MOV AX,#0xF000
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DELAY2:
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INC AX
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JNZ DELAY2
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INC DL
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JNZ DELAY21
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MOV BX,#0x0000
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MOV AX,#0x0200
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call sdram_dfii_pi0_address_write
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mov bx,#0x0000
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mov ax,#0x0002
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call sdram_dfii_pi0_baddress_write
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mov bx,#0x0000
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mov ax,#0x000F
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call command_p0
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MOV BX,#0x0000
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MOV AX,#0x0000
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call sdram_dfii_pi0_address_write
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mov bx,#0x0000
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mov ax,#0x0003
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call sdram_dfii_pi0_baddress_write
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mov bx,#0x0000
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mov ax,#0x000F
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call command_p0
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MOV BX,#0x0000
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MOV AX,#0x0006
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call sdram_dfii_pi0_address_write
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mov bx,#0x0000
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mov ax,#0x0001
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call sdram_dfii_pi0_baddress_write
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mov bx,#0x0000
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mov ax,#0x000F
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call command_p0
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MOV BX,#0x0000
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MOV AX,#0x0320
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call sdram_dfii_pi0_address_write
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mov bx,#0x0000
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mov ax,#0x0000
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call sdram_dfii_pi0_baddress_write
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mov bx,#0x0000
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mov ax,#0x000F
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call command_p0
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MOV DL,#0xF0
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DELAY31:
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MOV AX,#0xF000
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DELAY3:
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INC AX
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JNZ DELAY3
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INC DL
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JNZ DELAY31
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MOV BX,#0x0000
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MOV AX,#0x0400
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call sdram_dfii_pi0_address_write
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mov bx,#0x0000
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mov ax,#0x0000
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call sdram_dfii_pi0_baddress_write
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mov bx,#0x0000
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mov ax,#0x0003
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call command_p0
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;////sdram_software_control_off///
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MOV BX,#0x0000
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MOV AX,#0x0001
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call sdram_dfii_control_write
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;////////////////////////////////
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;Signify end of init
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MOV BX,#0x0000
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MOV AX,#0x0001
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CALL ddrctrl_init_done_write
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;;;;;;;;;; PROBABLY NOT NECESSARY
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MOV DL,#0xF0
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DELAY41:
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MOV AX,#0xF000
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DELAY4:
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INC AX
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JNZ DELAY4
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INC DL
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JNZ DELAY41
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;;; CHECK ;;;
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inw #0x20
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test al,#0x01
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jz failram
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mov bx,#OK_txt
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call print
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JMP FINISHED_DDR
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failram:
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mov bx,#FAIL_txt
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call print
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mov bx,#NOT_RDY_txt
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call print
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inw #0x20
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test al,#0x02
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jz skip_err
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mov bx,#ERR_ASRT_txt
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call print
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skip_err:
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inw #0x20
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test al,#0x04
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jnz skip_pll
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mov bx,#PLL_ERR_txt
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call print
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skip_pll:
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hlt
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FINISHED_DDR:
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MOV DI,#0x2000
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MOV AX,#0xAAAA
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MOV [DI],AX
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MOV [DI],AX
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MOV [DI],AX
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MOV [DI],AX
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MOV [DI],AX
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MOV [DI],AX
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MOV [DI],AX
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MOV [DI],AX
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MOV [DI],AX
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MOV [DI],AX
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MOV [DI],AX
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MOV AX,#0x6666
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MOV AX,[DI]
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CMP AX,#0xAAAA
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JNZ FAILED
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MOV BX,#MEMTEST_PASS
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CALL print
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MOV AL,#0x48
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MOV [DI],AX
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MOV AL,#0x00
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MOV AX,[DI]
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out byte #0xA5
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MOV DI,#0x3000
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MOV AL,#0x65
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MOV [DI],AX
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MOV AL,#0x00
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MOV AX,[DI]
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out byte #0xA5
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MOV DI,#0x4000
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MOV AL,#0x6c
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MOV [DI],AX
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MOV AL,#0x00
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MOV AX,[DI]
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out byte #0xA5
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MOV DI,#0x5000
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MOV AL,#0x6c
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MOV [DI],AX
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MOV AL,#0x00
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MOV AX,[DI]
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out byte #0xA5
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MOV DI,#0x6000
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MOV AL,#0x6f
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MOV [DI],AX
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MOV AL,#0x00
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MOV AX,[DI]
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out byte #0xA5
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HLT
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FAILED:
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MOV BX,#MEMTEST_FAIL
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CALL print
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MOV DL,#0xF0
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DELAY51:
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MOV AX,#0x5000
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DELAY5:
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INC AX
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JNZ DELAY5
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INC DL
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JNZ DELAY51
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MOV DI,#0x2000
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MOV AX,#0xAAAA
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||||
MOV [DI],AX
|
||||
MOV [DI],AX
|
||||
MOV [DI],AX
|
||||
MOV [DI],AX
|
||||
MOV [DI],AX
|
||||
MOV [DI],AX
|
||||
MOV [DI],AX
|
||||
MOV [DI],AX
|
||||
MOV [DI],AX
|
||||
MOV [DI],AX
|
||||
MOV [DI],AX
|
||||
MOV AX,#0x0000
|
||||
MOV AX,[DI]
|
||||
CMP AL,#0xAA
|
||||
JNZ FAILED2
|
||||
MOV BX,#MEMTEST_PASS
|
||||
CALL print
|
||||
HLT
|
||||
FAILED2:
|
||||
MOV BX,#MEMTEST_FAIL
|
||||
CALL print
|
||||
MOV AX,[DI]
|
||||
CMP AL,#0xAA
|
||||
JNZ FAILED3
|
||||
MOV BX,#MEMTEST_PASS
|
||||
CALL print
|
||||
HLT
|
||||
FAILED3:
|
||||
MOV BX,#MEMTEST_FAIL
|
||||
CALL print
|
||||
HLT
|
||||
|
||||
|
||||
;;; HELPER FUNCTION
|
||||
command_p0:
|
||||
call WISHBONE_SET_DATA
|
||||
MOV AX,#0x0401 ;ORIG=0x1804L
|
||||
CALL WISHBONE_SET_ADDRESS
|
||||
CALL DO_WRITE_TRANSACTION
|
||||
MOV AX,#0x0001
|
||||
MOV BX,#0x0000
|
||||
call WISHBONE_SET_DATA
|
||||
MOV AX,#0x0402 ;ORIG=0x1808L
|
||||
CALL WISHBONE_SET_ADDRESS
|
||||
CALL DO_WRITE_TRANSACTION
|
||||
ret
|
||||
|
||||
#AX: Lower 16 bits data
|
||||
#BX: Upper 16 bits data
|
||||
sdram_dfii_pi0_address_write:
|
||||
call WISHBONE_SET_DATA
|
||||
MOV AX,#0x0403 ;ORIG=0x180cL
|
||||
CALL WISHBONE_SET_ADDRESS
|
||||
CALL DO_WRITE_TRANSACTION
|
||||
ret
|
||||
|
||||
sdram_dfii_pi0_baddress_write:
|
||||
call WISHBONE_SET_DATA
|
||||
MOV AX,#0x0404 ;ORIG=0x1810L
|
||||
CALL WISHBONE_SET_ADDRESS
|
||||
CALL DO_WRITE_TRANSACTION
|
||||
ret
|
||||
|
||||
sdram_dfii_control_write:
|
||||
call WISHBONE_SET_DATA
|
||||
MOV AX,#0x0400 ;ORIG=0x1800L
|
||||
CALL WISHBONE_SET_ADDRESS
|
||||
CALL DO_WRITE_TRANSACTION
|
||||
ret
|
||||
|
||||
ddrctrl_init_done_write:
|
||||
call WISHBONE_SET_DATA
|
||||
MOV AX,#0x0000 ;ORIG=0x0L
|
||||
CALL WISHBONE_SET_ADDRESS
|
||||
CALL DO_WRITE_TRANSACTION
|
||||
ret
|
||||
|
||||
ddrctrl_init_error_write:
|
||||
call WISHBONE_SET_DATA
|
||||
MOV AX,#0x0001 ;ORIG=0x4L
|
||||
CALL WISHBONE_SET_ADDRESS
|
||||
CALL DO_WRITE_TRANSACTION
|
||||
ret
|
||||
;
|
||||
DO_WRITE_TRANSACTION:
|
||||
mov ax,#0x01
|
||||
outw #0x46
|
||||
mov bl,#0x01
|
||||
WB_WRITE_LOOP:
|
||||
inc bl
|
||||
jz WB_WRITE_TIMEOUT
|
||||
inw #0x44
|
||||
test al,#0x01
|
||||
jz WB_WRITE_LOOP
|
||||
test al,#0x04
|
||||
jnz WB_WRITE_ERR
|
||||
ret
|
||||
WB_WRITE_TIMEOUT:
|
||||
mov bx,#WISHBONE_TIMEOUT_txt
|
||||
call print
|
||||
hlt
|
||||
WB_WRITE_ERR:
|
||||
mov bx,#WISHBONE_ERROR_txt
|
||||
call print
|
||||
hlt
|
||||
|
||||
#AX: address
|
||||
WISHBONE_SET_ADDRESS:
|
||||
outw #0x44
|
||||
ret
|
||||
|
||||
#AX: Lower 16bits
|
||||
#BX: Upper 16bits
|
||||
WISHBONE_SET_DATA:
|
||||
outw #0x40
|
||||
MOV AX,BX
|
||||
outw #0x42
|
||||
ret
|
||||
INCLUDE dos_layer.asm
|
||||
include LiteDram_init.asm
|
||||
|
||||
print:
|
||||
mov al,[bx]
|
||||
@ -373,16 +19,6 @@ jmp print
|
||||
print_exit:
|
||||
ret
|
||||
|
||||
initdram_txt: .ASCII 'Init LiteDram: \0'
|
||||
OK_txt: .ASCII 'OK\n\0'
|
||||
PLL_ERR_txt: .ASCII 'PLL_ERR \0' ; PLL_ERR: pll_lock is not asserted
|
||||
ERR_ASRT_txt: .ASCII 'ERR_ASRT \0' ; ERR_ASRT: init_error is asserted
|
||||
NOT_RDY_txt: .ASCII 'NOT_RDY \0' ; NOT READY: init_done is not asserted
|
||||
FAIL_txt: .ASCII 'FAIL\n\0'
|
||||
WISHBONE_TIMEOUT_txt: .ASCII 'FAIL\nWISHBONE TIMEOUT\0'
|
||||
WISHBONE_ERROR_txt: .ASCII 'FAIL\nWISHBONE ERROR\0'
|
||||
MEMTEST_PASS: .ASCII 'MEMTEST PASSED\n\0'
|
||||
MEMTEST_FAIL: .ASCII 'MEMTEST FAILED\n\0'
|
||||
.BLKB 18 ; Using the text as stack space for the compiled program
|
||||
STACK: ; brainfuck_mandelbrot depends on stack being at the end
|
||||
|
||||
|
||||
@ -19,7 +19,7 @@
|
||||
|
||||
; 0x0000-0x0100 int vector 0x0100-0x0700 data 0x0700-0xC000 program data
|
||||
|
||||
mov sp,#STACK
|
||||
mov sp,#STACK_COMPILER
|
||||
mov bx,#bootup_msg
|
||||
mov ah,#0x02
|
||||
print1:
|
||||
@ -29,6 +29,14 @@ inc bx
|
||||
cmp dl,#0x0A
|
||||
jne print1
|
||||
|
||||
MOV DI,#0x0200
|
||||
MOV AX,#0x0000
|
||||
MOV bl,#0x00
|
||||
CLEAR:
|
||||
STOSW
|
||||
INC BL
|
||||
JNZ CLEAR
|
||||
|
||||
mov bx,#compiling
|
||||
mov ah,#0x02
|
||||
print2:
|
||||
@ -267,5 +275,5 @@ RET
|
||||
compiled: .ASCII '\rCompiled! \n'
|
||||
compiling: .ASCII 'Compiling...\0'
|
||||
bootup_msg: .ASCII 'Native 8086 brainfuck compiler v1\n'
|
||||
.BLKB 6 ; Using the text as stack space for the compiled program
|
||||
STACK: ; brainfuck_mandelbrot depends on stack being at the end
|
||||
.BLKB 10 ; Using the text as stack space for the compiled program
|
||||
STACK_COMPILER: ; brainfuck_mandelbrot depends on stack being at the end
|
||||
|
||||
Loading…
Reference in New Issue
Block a user