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Project: Removed some unused verilator warning restrictions and a TODO comment

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(Tim) Efthimis Kritikos 2023-12-06 02:46:39 +00:00
parent 05343864da
commit df5b9c13ea
3 changed files with 0 additions and 7 deletions
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4
system/biu.v
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@ -112,9 +112,7 @@ always @(posedge clock) begin
if (biu_state==`BIU_READ)
biu_state <= `BIU_NEXT_ACTION;
end else if(valid_instruction_ack) begin
/* verilator lint_off BLKSEQ */
FIFO_start <= FIFO_start + {{`L1_CACHE_SIZE-3{1'b0}},Isize};
/* verilator lint_on BLKSEQ */
INSTRUCTION_LOCATION <= INSTRUCTION_LOCATION + {13'd0,Isize};
end else if (wait_state==1)begin
// nothing...
@ -273,10 +271,8 @@ always @(posedge clock) begin
VALID_DATA <= 0;
end
`BIU_RESET2: begin
/* verilator lint_off BLKSEQ */
FIFO_start <= `L1_CACHE_SIZE'b0;
FIFO_end <= `L1_CACHE_SIZE'b0;
/* verilator lint_on BLKSEQ */
biu_state <= `BIU_NEXT_ACTION;
INSTRUCTION_ADDRESS <= 20'hFFFF0;
INSTRUCTION_LOCATION <= 16'hFFF0;

1
system/decoder.v
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@ -531,7 +531,6 @@ always @( posedge clock ) begin
PARAM_ACTION=`LOAD_16;
else begin
PARAM_ACTION=`LOAD_8;
//PARAM1[7:0]=INSTRUCTION[7:0]; TODO:needed?
end
next_state=`EXEC_WRITE_ENTRY;
`normal_instruction

2
system/system.v
View File

@ -173,9 +173,7 @@ end
/* instruction_count gets updated at the sme time as HALT is pulled so wait a clock cycle to get an accurate reading*/
$display("\x1b[7mProcessor halted.\nCycles run for : %0d\x1b[m",cycles);
`ifdef CALCULATE_IPC
/* verilator lint_off REALCVT */
$display("\x1b[7mInstr. per cycle : %f\x1b[m", $itor(instruction_count) / $itor(cycles) );
/* verilator lint_on REALCVT */
`endif
`ifdef OUTPUT_JSON_STATISTICS
instruction_count_temp <= instruction_count;