|
|
07d2a80b2e
|
Added code to record statistics and a tool to plot them
|
2023-05-14 16:06:33 +01:00 |
|
|
|
df342467c7
|
Saved a clock cycle from microcode starts and added info in decode to allow saving a cycle on almost every instruction
|
2023-05-13 13:45:15 +01:00 |
|
|
|
00aa828ddc
|
Improved parallelism
|
2023-05-13 10:52:44 +01:00 |
|
|
|
fe0426a77b
|
Made execute unit run in parallel with everything else. Still not parallel for most of the time though
|
2023-05-13 06:51:35 +01:00 |
|
|
|
7151d5634f
|
Fixed bug that prevented Icarus Verilog from simulating correctly
|
2023-05-11 19:55:47 +01:00 |
|
|
|
539fb8416b
|
Fixed copyright notices, did some major cleanup and bumped README's versions
|
2023-05-11 16:28:10 +01:00 |
|
|
|
a8ab6b2dc7
|
Separated the execution unit from decode
|
2023-05-11 12:22:49 +01:00 |
|
|
|
7724e5f383
|
Removed deprecated BIU_NEXT_POSITION
|
2023-05-10 08:53:29 +01:00 |
|
|
|
e4ef199b83
|
Fixed a memory corruption bug
|
2023-05-10 08:35:14 +01:00 |
|
|
|
7e612bb701
|
made BIU snoop into the processor to deliver new instructions faster and fixed some bugs
|
2023-05-10 08:31:14 +01:00 |
|
|
|
c854818d6d
|
Tightened up write timing
|
2023-05-10 04:43:09 +01:00 |
|
|
|
b7bfbd4e33
|
Improved BIU performance and debug messages
|
2023-05-10 04:05:56 +01:00 |
|
|
|
da51dd6da7
|
First draft of a bus interface unit in an effort to make the CPU pipelined. Currently supports code prefetching
|
2023-05-07 13:34:15 +01:00 |
|
|
|
88a47cc4a9
|
Slight change in REAMDE's wording
|
2023-05-04 03:47:25 +01:00 |
|
|
|
133bd33a9c
|
Added definition of the version names to README
|
2023-05-04 03:43:44 +01:00 |
|
|
|
f4b22951d0
|
Cleaned up some pieces of code and fixed a bug
|
2023-05-04 00:49:04 +01:00 |
|
|
|
1fd58fd62e
|
Added a background to the high level diagram picture to make it viewable on dark mode
|
2023-05-03 17:48:24 +01:00 |
|
|
|
bd7610879f
|
Removed erroneous file and run aspell
|
2023-03-21 14:51:39 +00:00 |
|
|
|
c25d2eaf19
|
Added a high level state diagram of the processor
|
2023-03-21 12:38:35 +00:00 |
|
|
|
2f9a8fa236
|
Improved DOS char print code
|
2023-03-14 07:20:30 +00:00 |
|
|
|
82baacfd5b
|
Fixed race condition giving garbage data on debug register write prints and ordering of reg write and instr fetch debug prints
|
2023-03-12 08:55:40 +00:00 |
|
|
|
9230900b75
|
fixed verilator lint warnings relating code enabled with debug options from config.v
|
2023-03-12 08:12:01 +00:00 |
|
|
|
aabe62b4c9
|
Added missing copyright and license notice
|
2023-03-09 06:13:34 +00:00 |
|
|
|
11624ca2d2
|
Added the OUT instruction to be able to properly address I/O and moved printing logic to a device on the I/O space. Also added IRET which is basically just a RET in this case
|
2023-03-09 06:03:13 +00:00 |
|
|
|
9de83fd7c1
|
Added partial support for the software interrupt INT instruction
|
2023-03-08 07:26:28 +00:00 |
|
|
|
d93c92c005
|
Slight adjustment to README
|
2023-03-06 21:57:36 +00:00 |
|
|
|
8070d4e58a
|
Improved build system's handling of verilator
|
2023-03-05 23:11:18 +00:00 |
|
|
|
e8b84a38b6
|
Updated README.md about verilator
|
2023-03-05 06:37:07 +00:00 |
|
|
|
99cbc49e95
|
Wrote a more complete testbench for verilator, switched from lx2 to fst and fixed cpu clock frequency calculation
|
2023-03-05 00:10:55 +00:00 |
|
|
|
5705b8e8a5
|
Added support for Verilator!
|
2023-03-04 08:37:43 +00:00 |
|
|
|
ba52ff89e6
|
Fixed most problems verilator's linter found
|
2023-03-04 06:22:28 +00:00 |
|
|
|
59ec1b7a15
|
Removed remnants of the old memory addressing system
|
2023-03-03 20:43:25 +00:00 |
|
|
|
b00cd988cf
|
Cleaned up boot_code
|
2023-03-03 19:36:28 +00:00 |
|
|
|
e1bb98c0f0
|
Updated toolchain versions and run project through aspell
|
2023-03-03 06:54:33 +00:00 |
|
|
|
f60084344e
|
Overhauled cpu frontend. Made memory byte addressable (necessary), cleaned up state machine and fixed small bug with MOV
|
2023-03-03 06:29:06 +00:00 |
|
|
|
70a9ce6368
|
Forgot to remove it from proc_state_def.v
|
2023-02-26 02:48:39 +00:00 |
|
|
|
f7d76f1944
|
Removed useless state in the state machine and ran the project through aspell
|
2023-02-26 02:46:43 +00:00 |
|
|
|
0c36e9d78c
|
Added message about compilation process on the compiler and fixed Makefile dependencies
|
2023-02-25 01:42:45 +00:00 |
|
|
|
6e8d951360
|
Increased the accessible memory and got the Mandelbrot renderer working under the brainfuck compiler!
|
2023-02-24 17:38:23 +00:00 |
|
|
|
6ea34a3525
|
Added MOV Immidiate to REG/MEM
|
2023-02-24 15:25:45 +00:00 |
|
|
|
5af6d720c3
|
Fixed ADD again and some memory read logic. Compiler runs the default brainfuck message program!!
|
2023-02-24 14:10:07 +00:00 |
|
|
|
3e484a0ceb
|
Added register indirect unconditional jump
|
2023-02-24 13:04:32 +00:00 |
|
|
|
9ed3dc3312
|
Fixed bug introduced in a previous commit about fixing ADD
|
2023-02-24 12:48:03 +00:00 |
|
|
|
96b7a4d298
|
Added the SUB instruction (piggybacking off of ADD) AND THE COMPILER FINISHES GENERATING CODE!!
|
2023-02-24 12:47:32 +00:00 |
|
|
|
808827cbdd
|
Fixed arg bug in ADD
|
2023-02-24 11:54:13 +00:00 |
|
|
|
355c673a37
|
Added a POP instruction
|
2023-02-24 11:31:15 +00:00 |
|
|
|
c3580848de
|
Added bitwise TEST instruction
|
2023-02-24 10:08:01 +00:00 |
|
|
|
abee49d6c3
|
Implemented PUSH instruction, fixed register addressing bug and a RET bug
|
2023-02-24 07:32:27 +00:00 |
|
|
|
a189da249c
|
Added STOS instruction. Native brainfuck compiler started generating code!
|
2023-02-24 05:01:55 +00:00 |
|
|
|
e684db8348
|
Added support to CMP for compare memory to opcode parameter, added support for both PROC_DE_LOAD_?_PARAM and PROC_MEMIO_READ at the same command and associated changes
|
2023-02-24 02:18:48 +00:00 |
|
