|
|
79d598fc64
|
Changed slogan and cleaned up some small pieces of code
|
2023-05-23 16:18:33 +01:00 |
|
|
|
0bf00df07c
|
Fixed clock cycle and instruction counter overflow
|
2023-05-23 09:27:46 +01:00 |
|
|
|
35a5a9ada2
|
Added more data to a test program
|
2023-05-22 22:33:00 +01:00 |
|
|
|
6c146098ee
|
Removed useless code from cache_fill_and_empty.asm
|
2023-05-21 03:01:24 +01:00 |
|
|
|
e74d73ed58
|
Added reporting of branches on the stat json files and improved the plotting script
|
2023-05-21 03:00:27 +01:00 |
|
|
|
3dd2ff59ea
|
Added 2 more test programs, 2 new instructions and fixed a bug in CMP
|
2023-05-21 01:48:50 +01:00 |
|
|
|
021dd06e9a
|
Added support for some more instructions, fixed a bug in CMP and also added a program that uses them
|
2023-05-19 17:59:20 +01:00 |
|
|
|
64f5da82b0
|
Improved cache utilisation plotting tool
|
2023-05-18 20:16:31 +01:00 |
|
|
|
1b510e4781
|
Made the size of the cache variable
|
2023-05-18 11:21:27 +01:00 |
|
|
|
7db70d79ff
|
Made execute unit start at a state transition of a signal from the decoder thus allowing for an IPC of 0.99 !!
|
2023-05-17 21:30:21 +01:00 |
|
|
|
90f63b525d
|
Made the decode unit able to continuously decode (simple) instructions if BIU allows it
|
2023-05-17 20:09:38 +01:00 |
|
|
|
30c3deca37
|
Made the execute unit signal the end of execution by a state change rather than the state of a signal to allow for one cycle instructions
|
2023-05-17 11:05:20 +01:00 |
|
|
|
53e9d371d7
|
Fully optimised BIU. Now it can instantly deliver instructions back to back
|
2023-05-16 18:07:28 +01:00 |
|
|
|
f914d1ec8f
|
Cleaned up processor.v a bit
|
2023-05-16 16:29:48 +01:00 |
|
|
|
aca3357cda
|
Fixed README formatting error
|
2023-05-16 14:06:17 +01:00 |
|
|
|
97912b1a29
|
Fixed bug found by icarus verilog and added outdated notice to README
|
2023-05-16 13:59:16 +01:00 |
|
|
|
bfa576e2a0
|
Cleaned up the interface between BIU and the processor
|
2023-05-16 13:33:08 +01:00 |
|
|
|
07d2a80b2e
|
Added code to record statistics and a tool to plot them
|
2023-05-14 16:06:33 +01:00 |
|
|
|
df342467c7
|
Saved a clock cycle from microcode starts and added info in decode to allow saving a cycle on almost every instruction
|
2023-05-13 13:45:15 +01:00 |
|
|
|
00aa828ddc
|
Improved parallelism
|
2023-05-13 10:52:44 +01:00 |
|
|
|
fe0426a77b
|
Made execute unit run in parallel with everything else. Still not parallel for most of the time though
|
2023-05-13 06:51:35 +01:00 |
|
|
|
7151d5634f
|
Fixed bug that prevented Icarus Verilog from simulating correctly
|
2023-05-11 19:55:47 +01:00 |
|
|
|
539fb8416b
|
Fixed copyright notices, did some major cleanup and bumped README's versions
|
2023-05-11 16:28:10 +01:00 |
|
|
|
a8ab6b2dc7
|
Separated the execution unit from decode
|
2023-05-11 12:22:49 +01:00 |
|
|
|
7724e5f383
|
Removed deprecated BIU_NEXT_POSITION
|
2023-05-10 08:53:29 +01:00 |
|
|
|
e4ef199b83
|
Fixed a memory corruption bug
|
2023-05-10 08:35:14 +01:00 |
|
|
|
7e612bb701
|
made BIU snoop into the processor to deliver new instructions faster and fixed some bugs
|
2023-05-10 08:31:14 +01:00 |
|
|
|
c854818d6d
|
Tightened up write timing
|
2023-05-10 04:43:09 +01:00 |
|
|
|
b7bfbd4e33
|
Improved BIU performance and debug messages
|
2023-05-10 04:05:56 +01:00 |
|
|
|
da51dd6da7
|
First draft of a bus interface unit in an effort to make the CPU pipelined. Currently supports code prefetching
|
2023-05-07 13:34:15 +01:00 |
|
|
|
88a47cc4a9
|
Slight change in REAMDE's wording
|
2023-05-04 03:47:25 +01:00 |
|
|
|
133bd33a9c
|
Added definition of the version names to README
|
2023-05-04 03:43:44 +01:00 |
|
|
|
f4b22951d0
|
Cleaned up some pieces of code and fixed a bug
|
2023-05-04 00:49:04 +01:00 |
|
|
|
1fd58fd62e
|
Added a background to the high level diagram picture to make it viewable on dark mode
|
2023-05-03 17:48:24 +01:00 |
|
|
|
bd7610879f
|
Removed erroneous file and run aspell
|
2023-03-21 14:51:39 +00:00 |
|
|
|
c25d2eaf19
|
Added a high level state diagram of the processor
|
2023-03-21 12:38:35 +00:00 |
|
|
|
2f9a8fa236
|
Improved DOS char print code
|
2023-03-14 07:20:30 +00:00 |
|
|
|
82baacfd5b
|
Fixed race condition giving garbage data on debug register write prints and ordering of reg write and instr fetch debug prints
|
2023-03-12 08:55:40 +00:00 |
|
|
|
9230900b75
|
fixed verilator lint warnings relating code enabled with debug options from config.v
|
2023-03-12 08:12:01 +00:00 |
|
|
|
aabe62b4c9
|
Added missing copyright and license notice
|
2023-03-09 06:13:34 +00:00 |
|
|
|
11624ca2d2
|
Added the OUT instruction to be able to properly address I/O and moved printing logic to a device on the I/O space. Also added IRET which is basically just a RET in this case
|
2023-03-09 06:03:13 +00:00 |
|
|
|
9de83fd7c1
|
Added partial support for the software interrupt INT instruction
|
2023-03-08 07:26:28 +00:00 |
|
|
|
d93c92c005
|
Slight adjustment to README
|
2023-03-06 21:57:36 +00:00 |
|
|
|
8070d4e58a
|
Improved build system's handling of verilator
|
2023-03-05 23:11:18 +00:00 |
|
|
|
e8b84a38b6
|
Updated README.md about verilator
|
2023-03-05 06:37:07 +00:00 |
|
|
|
99cbc49e95
|
Wrote a more complete testbench for verilator, switched from lx2 to fst and fixed cpu clock frequency calculation
|
2023-03-05 00:10:55 +00:00 |
|
|
|
5705b8e8a5
|
Added support for Verilator!
|
2023-03-04 08:37:43 +00:00 |
|
|
|
ba52ff89e6
|
Fixed most problems verilator's linter found
|
2023-03-04 06:22:28 +00:00 |
|
|
|
59ec1b7a15
|
Removed remnants of the old memory addressing system
|
2023-03-03 20:43:25 +00:00 |
|
|
|
b00cd988cf
|
Cleaned up boot_code
|
2023-03-03 19:36:28 +00:00 |
|
