Efthimis/9086
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A CPU that aims to be binary compatible with the 8086 ISA, focused on optimisation and flexibility.
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Verilog 66.9%
Makefile 9.9%
Assembly 9.4%
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(Tim) Efthimis Kritikos 7db70d79ff Made execute unit start at a state transition of a signal from the decoder thus allowing for an IPC of 0.99 !!
2023-05-17 21:30:21 +01:00
boot_code Added code to record statistics and a tool to plot them 2023-05-14 16:06:33 +01:00
readme_files Added a background to the high level diagram picture to make it viewable on dark mode 2023-05-03 17:48:24 +01:00
system Made execute unit start at a state transition of a signal from the decoder thus allowing for an IPC of 0.99 !! 2023-05-17 21:30:21 +01:00
tools Added code to record statistics and a tool to plot them 2023-05-14 16:06:33 +01:00
.gitignore Added code to record statistics and a tool to plot them 2023-05-14 16:06:33 +01:00
8086_documentation.md Overhauled cpu frontend. Made memory byte addressable (necessary), cleaned up state machine and fixed small bug with MOV 2023-03-03 06:29:06 +00:00
common.mk Added code to record statistics and a tool to plot them 2023-05-14 16:06:33 +01:00
COPYING Properly licensed the project and run it through aspell 2023-02-13 16:49:17 +00:00
gtkwave_savefile.gtkw Made the execute unit signal the end of execution by a state change rather than the state of a signal to allow for one cycle instructions 2023-05-17 11:05:20 +01:00
Makefile Added the OUT instruction to be able to properly address I/O and moved printing logic to a device on the I/O space. Also added IRET which is basically just a RET in this case 2023-03-09 06:03:13 +00:00
README.md Fixed README formatting error 2023-05-16 14:06:17 +01:00

README.md

9086 logo

A CPU that aims to be binary compatible with the 8086 and with as many optimisations as possible

Progress

  • 8086
    • Executing code
    • Is Turing complete
    • Can boot up MS-DOS / FreeDOS
    • Is completely binary compatible
    • Is pipelined
    • Is Out of Order
    • Is superscalar
    • Has been successfully synthesized

Simulating it

Both Verilator and Icarus Verilog can be used for simulation. You can select which one you want with the SIM variable on common.mk Specifically this list shows the software needed and the versions used during development (other versions should work as well)

  • Icarus Verilog : version 11.0 OR (preferred) Verilator : 5.008
  • bin86 : 0.16.21
  • GNU Make : 4.4.1
  • xxd : 2022-01-14
  • POSIX coreutils : GNU coreutils 9.3

After that you can run make on the top level directory and it should build everything and start the simulation

High level design overview

This image is outdated. It was made for v0.1.0

9086 logo

License

All parts of this project are licensed under the GNU General Public License version 3 or later

Version names

The version name consist of three numbers:

  1. The CPU that this version aims to be compatible with
  2. The specific milestone
  3. Patch level

For example v1.3.2 aims to support 80186 code, is on the fourth milestone and has 2 bug fixes since the milestone was reached.