Commit Graph

164 Commits

Author SHA1 Message Date
618c3102d8 Fixed some dependencies on the makefiles 2023-11-12 13:30:12 +00:00
7d2cb5672f Reduced numbers to be sorted in gnome_sort.asm to fit in lcd, fixed hlt on real hardware, slowed down cpu, increased lcd fifo and with that I almost got gnome_sort.asm working perfectly on real hardware 2023-11-12 07:31:05 +00:00
e06c0eeaa0 Made the build system simplify the microcode so that yosys understands and synthesises it! Now gnome_sort.asm almost works! 2023-11-12 04:04:56 +00:00
fa62b07c14 Removed probably unnecessary high impedance case yosys was complaining about in registers.v 2023-11-12 03:13:22 +00:00
f471b305d8 Switched some assignments in decode.v to non-blocking which fixed a seemingly unrelated bug with incrementing the accumulator, added some more working test code in colored_led.asm and did some semantic changes as per yosys suggestions 2023-11-12 02:54:41 +00:00
4c130a8d63 Added back removed warnings to verilator since we have now fixed those issues 2023-11-12 00:07:33 +00:00
09b3d51015 Added statistics to place&route 2023-11-09 23:10:06 +00:00
863af26422 Forgot to add the changes to colored_led.asm from the previous commit 2023-11-09 23:08:12 +00:00
a88c420ca5 Added an I2C driver, a PCF8574 driver and an HD44780 display driver. Unfortunately this shows that even fibonacci doesn't run correctly. Nonetheless, I made colored_led.asm output text to the display! 2023-11-09 22:10:55 +00:00
e0dc7bae07 Move the diagram below some text since it looks a bit ugly this way 2023-11-07 14:40:51 +00:00
1a1634c673 Updated README, improved fpga-specific makefile options and updated the version number 2023-11-07 14:37:22 +00:00
4767a7addc Updated progress on README 2023-11-06 08:18:19 +00:00
01dcbfa7a1 The CPU works on real hardware for the first time! I added an adjustment for ram size, added control for a led and a test program for it. On the fpga board there is an actual led there that I used to verify functionality 2023-11-06 08:13:36 +00:00
30ffa1b00c Fixed a "combinatorial loop" and now if the build-in memory is reduced the design can be synthesized! 2023-11-06 05:36:04 +00:00
5ebd53b11c fixed more driver conflicts 2023-11-06 01:35:48 +00:00
ae16c79b0a Fixed another driver conflict 2023-11-05 20:18:11 +00:00
9947517693 Fixed simulation with icarus verilog and removed another driver conflict 2023-11-05 19:43:49 +00:00
4a5df9c74e Fixed another driver conflict 2023-11-05 16:23:05 +00:00
aa9b7c0a50 Removed more "conflicting driver" issues with yet more performance penalties... 2023-11-04 15:33:23 +00:00
df2975fa09 Fixed a lot of "conflicting driver" issues but I had to roll back an optimisation 2023-11-04 11:04:22 +00:00
c7ddf3fa9e More small fixes 2023-11-04 08:31:05 +00:00
694f708a32 Fixed some relatively low hanging fruit 2023-11-04 08:08:22 +00:00
934e2f5a36 Fixed a bunch of things wrong with fpga_top.v and gated off some more simulation-only code 2023-11-02 23:46:12 +00:00
08aac5c7b6 Removed some code that wasn't meant for synthesis and fixed important bug in Makefile 2023-11-02 22:19:15 +00:00
601397b7f0 Properly added fpga_top.v stuff in the build system and fixed some syntax errors 2023-11-02 22:00:07 +00:00
43f3e16ca4 Removed all instances of inout since from what i understand it's mostly synthesisable 2023-11-02 21:48:12 +00:00
36bf8f9c7a Added OrangeCrab board-specific code to connect the cpu to the outside world 2023-11-02 20:40:04 +00:00
5feee9de57 Added support to the build system for synthesising, place and routing, serialising and uploading the design to a Lattice ECP5 OrangeCrab FPGA 2023-11-02 00:29:14 +00:00
85512d5ace Last minute fix of dependencies in Makefile before release 2023-11-01 19:09:59 +00:00
b2972c9938 release v0.2.0 - Pipelined milestone 2023-11-01 06:08:12 +00:00
3ec90b1843 Added version stamp and last commit to json log 2023-11-01 06:03:53 +00:00
557d160be6 did some cleanup relating to the generation of the VALID_INSTRUCTION signal 2023-11-01 05:00:09 +00:00
3a63e916f5 Added cycles to waveform capture for icarus verilog 2023-10-31 19:32:35 +00:00
49335a2c2f Fixed a small bug in log generation and did some cleanup 2023-10-31 19:01:34 +00:00
8a62b89a13 Fixed small bug with json data reporting and improved slightly the graphs 2023-10-30 08:01:03 +00:00
cfed0b4117 Made the temporary logo a bit more centered. Also removed an incorrect line in README 2023-10-24 01:08:13 +01:00
4c28f98797 Updated the high level design overview diagram 2023-10-23 13:28:58 +01:00
d151435ac1 Removed redundant checks for enabled early instruction detection in BIU 2023-10-23 02:30:25 +01:00
ced03c48d6 Added cache flush after write, potentially fixing support for self modifying code 2023-10-23 02:09:13 +01:00
8d3b54b812 Small change from when I last worked on this and an update to the versions on the README 2023-10-21 18:38:50 +01:00
42c319d55d Lots of cleanup mainly on processor.v 2023-06-01 02:13:55 +01:00
a693b87e96 General cleanup and moved the reading of instruction parameters from a separate stage in execute to circuitry during the decode 2023-05-29 02:29:15 +01:00
af63ef1d68 Moved the decoder logic to decoder.v Now processor.v only connects the different modules 2023-05-27 23:35:00 +01:00
d2a98c02ff Removed duplicate code and improved microcode entry 2023-05-27 17:59:52 +01:00
79d598fc64 Changed slogan and cleaned up some small pieces of code 2023-05-23 16:18:33 +01:00
0bf00df07c Fixed clock cycle and instruction counter overflow 2023-05-23 09:27:46 +01:00
35a5a9ada2 Added more data to a test program 2023-05-22 22:33:00 +01:00
6c146098ee Removed useless code from cache_fill_and_empty.asm 2023-05-21 03:01:24 +01:00
e74d73ed58 Added reporting of branches on the stat json files and improved the plotting script 2023-05-21 03:00:27 +01:00
3dd2ff59ea Added 2 more test programs, 2 new instructions and fixed a bug in CMP 2023-05-21 01:48:50 +01:00