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A CPU that aims to be binary compatible with the 8086 ISA, focused on optimisation and flexibility.
123 Commits 2 Branches 4 Tags 1.8 MiB
Verilog 66.9%
Makefile 9.9%
Assembly 9.4%
Shell 6.9%
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(Tim) Efthimis Kritikos a693b87e96 General cleanup and moved the reading of instruction parameters from a separate stage in execute to circuitry during the decode
2023-05-29 02:29:15 +01:00
boot_code Added more data to a test program 2023-05-22 22:33:00 +01:00
readme_files Added a background to the high level diagram picture to make it viewable on dark mode 2023-05-03 17:48:24 +01:00
system General cleanup and moved the reading of instruction parameters from a separate stage in execute to circuitry during the decode 2023-05-29 02:29:15 +01:00
tools Added reporting of branches on the stat json files and improved the plotting script 2023-05-21 03:00:27 +01:00
.gitignore Added support for some more instructions, fixed a bug in CMP and also added a program that uses them 2023-05-19 17:59:20 +01:00
8086_documentation.md Changed slogan and cleaned up some small pieces of code 2023-05-23 16:18:33 +01:00
common.mk Added code to record statistics and a tool to plot them 2023-05-14 16:06:33 +01:00
COPYING Properly licensed the project and run it through aspell 2023-02-13 16:49:17 +00:00
gtkwave_savefile.gtkw Made the execute unit signal the end of execution by a state change rather than the state of a signal to allow for one cycle instructions 2023-05-17 11:05:20 +01:00
Makefile Added 2 more test programs, 2 new instructions and fixed a bug in CMP 2023-05-21 01:48:50 +01:00
README.md Changed slogan and cleaned up some small pieces of code 2023-05-23 16:18:33 +01:00

README.md

9086 logo

A CPU that aims to be binary compatible with the 8086 ISA, focused on optimisation and flexibility.

Progress

  • 8086
    • Executing code
    • Is Turing complete
    • Can boot up MS-DOS / FreeDOS
    • Is completely binary compatible
    • Is pipelined
    • Is Out of Order
    • Is superscalar
    • Has been successfully synthesized

Simulating it

Both Verilator and Icarus Verilog can be used for simulation. You can select which one you want with the SIM variable on common.mk Specifically this list shows the software needed and the versions used during development (other versions should work as well)

  • Icarus Verilog : version 11.0 OR (preferred) Verilator : 5.008
  • bin86 : 0.16.21
  • GNU Make : 4.4.1
  • xxd : 2022-01-14
  • POSIX coreutils : GNU coreutils 9.3

After that you can run make on the top level directory and it should build everything and start the simulation

High level design overview

This image is outdated. It was made for v0.1.0

9086 logo

License

All parts of this project are licensed under the GNU General Public License version 3 or later

Version names

The version name consist of three numbers:

  1. The CPU that this version aims to be compatible with
  2. The specific milestone
  3. Patch level

For example v1.3.2 aims to support 80186 code, is on the fourth milestone and has 2 bug fixes since the milestone was reached.