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0bf00df07c
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Fixed clock cycle and instruction counter overflow
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2023-05-23 09:27:46 +01:00 |
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35a5a9ada2
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Added more data to a test program
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2023-05-22 22:33:00 +01:00 |
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6c146098ee
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Removed useless code from cache_fill_and_empty.asm
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2023-05-21 03:01:24 +01:00 |
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e74d73ed58
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Added reporting of branches on the stat json files and improved the plotting script
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2023-05-21 03:00:27 +01:00 |
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3dd2ff59ea
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Added 2 more test programs, 2 new instructions and fixed a bug in CMP
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2023-05-21 01:48:50 +01:00 |
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021dd06e9a
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Added support for some more instructions, fixed a bug in CMP and also added a program that uses them
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2023-05-19 17:59:20 +01:00 |
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64f5da82b0
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Improved cache utilisation plotting tool
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2023-05-18 20:16:31 +01:00 |
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1b510e4781
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Made the size of the cache variable
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2023-05-18 11:21:27 +01:00 |
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7db70d79ff
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Made execute unit start at a state transition of a signal from the decoder thus allowing for an IPC of 0.99 !!
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2023-05-17 21:30:21 +01:00 |
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90f63b525d
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Made the decode unit able to continuously decode (simple) instructions if BIU allows it
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2023-05-17 20:09:38 +01:00 |
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30c3deca37
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Made the execute unit signal the end of execution by a state change rather than the state of a signal to allow for one cycle instructions
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2023-05-17 11:05:20 +01:00 |
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53e9d371d7
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Fully optimised BIU. Now it can instantly deliver instructions back to back
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2023-05-16 18:07:28 +01:00 |
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f914d1ec8f
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Cleaned up processor.v a bit
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2023-05-16 16:29:48 +01:00 |
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aca3357cda
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Fixed README formatting error
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2023-05-16 14:06:17 +01:00 |
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97912b1a29
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Fixed bug found by icarus verilog and added outdated notice to README
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2023-05-16 13:59:16 +01:00 |
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bfa576e2a0
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Cleaned up the interface between BIU and the processor
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2023-05-16 13:33:08 +01:00 |
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07d2a80b2e
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Added code to record statistics and a tool to plot them
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2023-05-14 16:06:33 +01:00 |
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df342467c7
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Saved a clock cycle from microcode starts and added info in decode to allow saving a cycle on almost every instruction
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2023-05-13 13:45:15 +01:00 |
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00aa828ddc
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Improved parallelism
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2023-05-13 10:52:44 +01:00 |
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fe0426a77b
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Made execute unit run in parallel with everything else. Still not parallel for most of the time though
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2023-05-13 06:51:35 +01:00 |
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7151d5634f
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Fixed bug that prevented Icarus Verilog from simulating correctly
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2023-05-11 19:55:47 +01:00 |
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539fb8416b
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Fixed copyright notices, did some major cleanup and bumped README's versions
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2023-05-11 16:28:10 +01:00 |
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a8ab6b2dc7
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Separated the execution unit from decode
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2023-05-11 12:22:49 +01:00 |
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7724e5f383
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Removed deprecated BIU_NEXT_POSITION
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2023-05-10 08:53:29 +01:00 |
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e4ef199b83
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Fixed a memory corruption bug
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2023-05-10 08:35:14 +01:00 |
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7e612bb701
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made BIU snoop into the processor to deliver new instructions faster and fixed some bugs
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2023-05-10 08:31:14 +01:00 |
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c854818d6d
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Tightened up write timing
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2023-05-10 04:43:09 +01:00 |
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b7bfbd4e33
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Improved BIU performance and debug messages
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2023-05-10 04:05:56 +01:00 |
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da51dd6da7
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First draft of a bus interface unit in an effort to make the CPU pipelined. Currently supports code prefetching
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2023-05-07 13:34:15 +01:00 |
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88a47cc4a9
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Slight change in REAMDE's wording
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2023-05-04 03:47:25 +01:00 |
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133bd33a9c
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Added definition of the version names to README
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2023-05-04 03:43:44 +01:00 |
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f4b22951d0
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Cleaned up some pieces of code and fixed a bug
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2023-05-04 00:49:04 +01:00 |
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1fd58fd62e
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Added a background to the high level diagram picture to make it viewable on dark mode
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2023-05-03 17:48:24 +01:00 |
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bd7610879f
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Removed erroneous file and run aspell
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2023-03-21 14:51:39 +00:00 |
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c25d2eaf19
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Added a high level state diagram of the processor
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2023-03-21 12:38:35 +00:00 |
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2f9a8fa236
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Improved DOS char print code
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2023-03-14 07:20:30 +00:00 |
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82baacfd5b
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Fixed race condition giving garbage data on debug register write prints and ordering of reg write and instr fetch debug prints
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2023-03-12 08:55:40 +00:00 |
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9230900b75
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fixed verilator lint warnings relating code enabled with debug options from config.v
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2023-03-12 08:12:01 +00:00 |
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aabe62b4c9
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Added missing copyright and license notice
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2023-03-09 06:13:34 +00:00 |
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11624ca2d2
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Added the OUT instruction to be able to properly address I/O and moved printing logic to a device on the I/O space. Also added IRET which is basically just a RET in this case
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2023-03-09 06:03:13 +00:00 |
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9de83fd7c1
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Added partial support for the software interrupt INT instruction
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2023-03-08 07:26:28 +00:00 |
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d93c92c005
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Slight adjustment to README
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2023-03-06 21:57:36 +00:00 |
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8070d4e58a
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Improved build system's handling of verilator
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2023-03-05 23:11:18 +00:00 |
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e8b84a38b6
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Updated README.md about verilator
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2023-03-05 06:37:07 +00:00 |
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99cbc49e95
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Wrote a more complete testbench for verilator, switched from lx2 to fst and fixed cpu clock frequency calculation
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2023-03-05 00:10:55 +00:00 |
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5705b8e8a5
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Added support for Verilator!
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2023-03-04 08:37:43 +00:00 |
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ba52ff89e6
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Fixed most problems verilator's linter found
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2023-03-04 06:22:28 +00:00 |
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59ec1b7a15
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Removed remnants of the old memory addressing system
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2023-03-03 20:43:25 +00:00 |
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b00cd988cf
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Cleaned up boot_code
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2023-03-03 19:36:28 +00:00 |
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e1bb98c0f0
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Updated toolchain versions and run project through aspell
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2023-03-03 06:54:33 +00:00 |
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