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aeba97df05
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Didn't add all files on last commit
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2023-02-07 17:58:07 +00:00 |
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a13ffe57b6
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Fixed VPP typo. should be VVP
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2023-02-07 17:55:57 +00:00 |
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d8f6c595a2
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Added clock and gtkwave integration
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2023-02-07 17:52:02 +00:00 |
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b749a5610e
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Fixed git ignore and cleanup
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2023-02-06 21:09:55 +00:00 |
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a0c2413b85
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First try at the Verilog VPI
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2023-02-06 15:42:39 +00:00 |
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9b350ec117
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Wrote my first verilog project ( a multiplexer ) with a testbench and added a .gitignore
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2023-01-24 20:27:15 +00:00 |
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fb8208ef55
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Dipping my toes into verilog development
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2023-01-24 16:21:59 +00:00 |
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