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• aeba97df05 Didn't add all files on last commit master (Tim) Efthymios Kritikos 2023-02-07 17:58:07 +0000
• a13ffe57b6 Fixed VPP typo. should be VVP (Tim) Efthymios Kritikos 2023-02-07 17:55:57 +0000
• d8f6c595a2 Added clock and gtkwave integration (Tim) Efthymios Kritikos 2023-02-07 17:52:02 +0000
• b749a5610e Fixed git ignore and cleanup (Tim) Efthymios Kritikos 2023-02-06 21:09:55 +0000
• a0c2413b85 First try at the Verilog VPI (Tim) Efthymios Kritikos 2023-02-06 15:42:39 +0000
• 9b350ec117 Wrote my first verilog project ( a multiplexer ) with a testbench and added a .gitignore (Tim) Efthymios Kritikos 2023-01-24 20:27:15 +0000
• fb8208ef55 Dipping my toes into verilog development (Tim) Efthymios Kritikos 2023-01-24 16:21:59 +0000