(Tim) Efthymios Kritikos a0c2413b85 First try at the Verilog VPI		2023-02-06 15:42:39 +00:00
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counter	Dipping my toes into verilog development	2023-01-24 16:21:59 +00:00
hello_world	Dipping my toes into verilog development	2023-01-24 16:21:59 +00:00
multiplexer	Wrote my first verilog project ( a multiplexer ) with a testbench and added a .gitignore	2023-01-24 20:27:15 +00:00
VPI_example	First try at the Verilog VPI	2023-02-06 15:42:39 +00:00