Efthimis/COMS30046_2022_TB-2_playground
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Wrote my first verilog project ( a multiplexer ) with a testbench and added a .gitignore

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(Tim) Efthymios Kritikos 2023-01-24 20:27:15 +00:00
parent fb8208ef55
commit 9b350ec117
4 changed files with 70 additions and 0 deletions
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1
.gitignore vendored Normal file
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*.vpp

11
verilog_iverilog/multiplexer/Makefile Normal file
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SOURCES=multiplexer.v multiplexer-tb.v
VPP=multiplexer.vpp
run: ${VPP}
vvp ${VPP}
${VPP} : ${SOURCES}
iverilog $^ -o $@
clean:
rm -f ${VPP}

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verilog_iverilog/multiplexer/multiplexer-tb.v Normal file
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module hello;
wire out;
reg A,B,X;
multiplexer idk(A,B,X,out);
initial
begin
$display("RSLT\tOUT\tA\tB\tSLCT");
A=1;B=1;X=1;#50
if(out==1)
$display("PASS\t%b\t%b\t%b\t%b",out,A,B,X);
else
$display("FAIL\t%b\t%b\t%b\t%b",out,A,B,X);
A=1;B=0;X=1;#50
if(out==0)
$display("PASS\t%b\t%b\t%b\t%b",out,A,B,X);
else
$display("FAIL\t%b\t%b\t%b\t%b",out,A,B,X);
A=0;B=1;X=1;#50
if(out==1)
$display("PASS\t%b\t%b\t%b\t%b",out,A,B,X);
else
$display("FAIL\t%b\t%b\t%b\t%b",out,A,B,X);
A=0;B=0;X=1;#50
if(out==0)
$display("PASS\t%b\t%b\t%b\t%b",out,A,B,X);
else
$display("FAIL\t%b\t%b\t%b\t%b",out,A,B,X);
A=1;B=1;X=0;#50
if(out==1)
$display("PASS\t%b\t%b\t%b\t%b",out,A,B,X);
else
$display("FAIL\t%b\t%b\t%b\t%b",out,A,B,X);
A=1;B=0;X=0;#50
if(out==1)
$display("PASS\t%b\t%b\t%b\t%b",out,A,B,X);
else
$display("FAIL\t%b\t%b\t%b\t%b",out,A,B,X);
A=0;B=1;X=0;#50
if(out==0)
$display("PASS\t%b\t%b\t%b\t%b",out,A,B,X);
else
$display("FAIL\t%b\t%b\t%b\t%b",out,A,B,X);
A=0;B=0;X=0;#50
if(out==0)
$display("PASS\t%b\t%b\t%b\t%b",out,A,B,X);
else
$display("FAIL\t%b\t%b\t%b\t%b",out,A,B,X);
$finish ;
end
endmodule

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verilog_iverilog/multiplexer/multiplexer.v Normal file
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module multiplexer(A,B,X,out1);
input A,B,X;
output out1;
assign out1 = (~X&A)|(B&X);
endmodule