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Fixed VPP typo. should be VVP

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(Tim) Efthymios Kritikos 2023-02-07 17:55:57 +00:00
parent d8f6c595a2
commit a13ffe57b6
1 changed files with 0 additions and 581 deletions
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581
verilog_iverilog/clock/clock.vpp
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@ -1,581 +0,0 @@
#! /usr/bin/vvp
:ivl_version "11.0 (stable)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision - 12;
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2009.vpi";
S_0x5610fda4b6d0 .scope package, "$unit" "$unit" 2 1;
.timescale 0 0;
S_0x5610fda4b860 .scope module, "tb" "tb" 3 1;
.timescale -9 -12;
v0x5610fda78da0_0 .net "clk1", 0 0, v0x5610fda53880_0; 1 drivers
v0x5610fda78e40_0 .net "clk2", 0 0, v0x5610fda76fe0_0; 1 drivers
v0x5610fda78f10_0 .net "clk3", 0 0, v0x5610fda77b40_0; 1 drivers
v0x5610fda79010_0 .net "clk4", 0 0, v0x5610fda786e0_0; 1 drivers
v0x5610fda790e0_0 .var "delay", 7 0;
v0x5610fda791d0_0 .var "enable", 0 0;
v0x5610fda79270_0 .var/i "i", 31 0;
S_0x5610fda44700 .scope module, "u0" "clock_gen" 3 9, 4 3 0, S_0x5610fda4b860;
.timescale -9 -12;
.port_info 0 /INPUT 1 "enable";
.port_info 1 /OUTPUT 1 "clk";
P_0x5610fda0ca60 .param/l "DUTY" 0 4 7, +C4<00000000000000000000000000110010>;
P_0x5610fda0caa0 .param/l "FREQ" 0 4 5, +C4<00000000000000000000001111101000>;
P_0x5610fda0cae0 .param/l "PHASE" 0 4 6, +C4<00000000000000000000000000000000>;
v0x5610fda53880_0 .var "clk", 0 0;
v0x5610fda53920_0 .var/real "clk_off", 0 0;
v0x5610fda42f50_0 .var/real "clk_on", 0 0;
v0x5610fda42ff0_0 .var/real "clk_pd", 0 0;
v0x5610fda3e7e0_0 .net "enable", 0 0, v0x5610fda791d0_0; 1 drivers
v0x5610fda3e880_0 .var/real "quarter", 0 0;
v0x5610fda769f0_0 .var "start_clk", 0 0;
v0x5610fda76ab0_0 .var/real "start_dly", 0 0;
E_0x5610fda468c0 .event posedge, v0x5610fda769f0_0;
E_0x5610fda47160/0 .event negedge, v0x5610fda3e7e0_0;
E_0x5610fda47160/1 .event posedge, v0x5610fda3e7e0_0;
E_0x5610fda47160 .event/or E_0x5610fda47160/0, E_0x5610fda47160/1;
S_0x5610fda76bd0 .scope module, "u1" "clock_gen" 3 10, 4 3 0, S_0x5610fda4b860;
.timescale -9 -12;
.port_info 0 /INPUT 1 "enable";
.port_info 1 /OUTPUT 1 "clk";
P_0x5610fda76db0 .param/l "DUTY" 0 4 7, +C4<00000000000000000000000000110010>;
P_0x5610fda76df0 .param/l "FREQ" 0 4 5, +C4<00000000000000011000011010100000>;
P_0x5610fda76e30 .param/l "PHASE" 0 4 6, +C4<00000000000000000000000000000000>;
v0x5610fda76fe0_0 .var "clk", 0 0;
v0x5610fda770c0_0 .var/real "clk_off", 0 0;
v0x5610fda77180_0 .var/real "clk_on", 0 0;
v0x5610fda77250_0 .var/real "clk_pd", 0 0;
v0x5610fda77310_0 .net "enable", 0 0, v0x5610fda791d0_0; alias, 1 drivers
v0x5610fda77400_0 .var/real "quarter", 0 0;
v0x5610fda774a0_0 .var "start_clk", 0 0;
v0x5610fda77560_0 .var/real "start_dly", 0 0;
E_0x5610fda2f6d0 .event posedge, v0x5610fda774a0_0;
S_0x5610fda77680 .scope module, "u2" "clock_gen" 3 11, 4 3 0, S_0x5610fda4b860;
.timescale -9 -12;
.port_info 0 /INPUT 1 "enable";
.port_info 1 /OUTPUT 1 "clk";
P_0x5610fda77890 .param/l "DUTY" 0 4 7, +C4<00000000000000000000000000110010>;
P_0x5610fda778d0 .param/l "FREQ" 0 4 5, +C4<00000000000000110000110101000000>;
P_0x5610fda77910 .param/l "PHASE" 0 4 6, +C4<00000000000000000000000000000000>;
v0x5610fda77b40_0 .var "clk", 0 0;
v0x5610fda77c20_0 .var/real "clk_off", 0 0;
v0x5610fda77ce0_0 .var/real "clk_on", 0 0;
v0x5610fda77db0_0 .var/real "clk_pd", 0 0;
v0x5610fda77e70_0 .net "enable", 0 0, v0x5610fda791d0_0; alias, 1 drivers
v0x5610fda77fb0_0 .var/real "quarter", 0 0;
v0x5610fda78070_0 .var "start_clk", 0 0;
v0x5610fda78130_0 .var/real "start_dly", 0 0;
E_0x5610fda77ae0 .event posedge, v0x5610fda78070_0;
S_0x5610fda78250 .scope module, "u3" "clock_gen" 3 12, 4 3 0, S_0x5610fda4b860;
.timescale -9 -12;
.port_info 0 /INPUT 1 "enable";
.port_info 1 /OUTPUT 1 "clk";
P_0x5610fda78430 .param/l "DUTY" 0 4 7, +C4<00000000000000000000000000110010>;
P_0x5610fda78470 .param/l "FREQ" 0 4 5, +C4<00000000000001100001101010000000>;
P_0x5610fda784b0 .param/l "PHASE" 0 4 6, +C4<00000000000000000000000000000000>;
v0x5610fda786e0_0 .var "clk", 0 0;
v0x5610fda787c0_0 .var/real "clk_off", 0 0;
v0x5610fda78880_0 .var/real "clk_on", 0 0;
v0x5610fda78950_0 .var/real "clk_pd", 0 0;
v0x5610fda78a10_0 .net "enable", 0 0, v0x5610fda791d0_0; alias, 1 drivers
v0x5610fda78b00_0 .var/real "quarter", 0 0;
v0x5610fda78bc0_0 .var "start_clk", 0 0;
v0x5610fda78c80_0 .var/real "start_dly", 0 0;
E_0x5610fda78660 .event posedge, v0x5610fda78bc0_0;
.scope S_0x5610fda44700;
T_0 ;
%pushi/real 2097152000, 4075; load=1000.00
%store/real v0x5610fda42ff0_0;
%pushi/real 1073741824, 4065; load=0.500000
%load/real v0x5610fda42ff0_0;
%mul/wr;
%store/real v0x5610fda42f50_0;
%pushi/real 1073741824, 4065; load=0.500000
%load/real v0x5610fda42ff0_0;
%mul/wr;
%store/real v0x5610fda53920_0;
%load/real v0x5610fda42ff0_0;
%pushi/vec4 4, 0, 32;
%cvt/rv/s;
%div/wr;
%store/real v0x5610fda3e880_0;
%load/real v0x5610fda3e880_0;
%pushi/vec4 0, 0, 32;
%cvt/rv/s;
%mul/wr;
%pushi/vec4 90, 0, 32;
%cvt/rv/s;
%div/wr;
%store/real v0x5610fda76ab0_0;
%end;
.thread T_0, $init;
.scope S_0x5610fda44700;
T_1 ;
%vpi_call/w 4 18 "$display", "FREQ = %0d kHz", P_0x5610fda0caa0 {0 0 0};
%vpi_call/w 4 19 "$display", "PHASE = %0d deg", P_0x5610fda0cae0 {0 0 0};
%vpi_call/w 4 20 "$display", "DUTY = %0d %%", P_0x5610fda0ca60 {0 0 0};
%vpi_call/w 4 22 "$display", "PERIOD = %0.1f ms", v0x5610fda42ff0_0 {0 0 0};
%vpi_call/w 4 23 "$display", "CLK_ON = %0.1f ms", v0x5610fda42f50_0 {0 0 0};
%vpi_call/w 4 24 "$display", "CLK_OFF = %0.1f ms", v0x5610fda53920_0 {0 0 0};
%vpi_call/w 4 25 "$display", "QUARTER = %0.1f ms", v0x5610fda3e880_0 {0 0 0};
%vpi_call/w 4 26 "$display", "START_DLY = %0.1f ms", v0x5610fda76ab0_0 {0 0 0};
%end;
.thread T_1;
.scope S_0x5610fda44700;
T_2 ;
%pushi/vec4 0, 0, 1;
%assign/vec4 v0x5610fda53880_0, 0;
%pushi/vec4 0, 0, 1;
%assign/vec4 v0x5610fda769f0_0, 0;
%end;
.thread T_2;
.scope S_0x5610fda44700;
T_3 ;
%wait E_0x5610fda47160;
%load/vec4 v0x5610fda3e7e0_0;
%flag_set/vec4 8;
%jmp/0xz T_3.0, 8;
%load/real v0x5610fda76ab0_0;
%pushi/real 2097152000, 4075; load=1000.00
%mul/wr;
%cvt/vr 64;
%muli 1, 0, 64;
%ix/vec4 4;
%delayx 4;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x5610fda769f0_0, 0, 1;
%jmp T_3.1;
T_3.0 ;
%load/real v0x5610fda76ab0_0;
%pushi/real 2097152000, 4075; load=1000.00
%mul/wr;
%cvt/vr 64;
%muli 1, 0, 64;
%ix/vec4 4;
%delayx 4;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x5610fda769f0_0, 0, 1;
T_3.1 ;
%jmp T_3;
.thread T_3;
.scope S_0x5610fda44700;
T_4 ;
%wait E_0x5610fda468c0;
%load/vec4 v0x5610fda769f0_0;
%flag_set/vec4 8;
%jmp/0xz T_4.0, 8;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x5610fda53880_0, 0, 1;
T_4.2 ;
%load/vec4 v0x5610fda769f0_0;
%flag_set/vec4 8;
%jmp/0xz T_4.3, 8;
%load/real v0x5610fda42f50_0;
%pushi/real 2097152000, 4075; load=1000.00
%mul/wr;
%cvt/vr 64;
%muli 1, 0, 64;
%ix/vec4 4;
%delayx 4;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x5610fda53880_0, 0, 1;
%load/real v0x5610fda53920_0;
%pushi/real 2097152000, 4075; load=1000.00
%mul/wr;
%cvt/vr 64;
%muli 1, 0, 64;
%ix/vec4 4;
%delayx 4;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x5610fda53880_0, 0, 1;
%jmp T_4.2;
T_4.3 ;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x5610fda53880_0, 0, 1;
T_4.0 ;
%jmp T_4;
.thread T_4;
.scope S_0x5610fda76bd0;
T_5 ;
%pushi/real 1342177280, 4069; load=10.0000
%store/real v0x5610fda77250_0;
%pushi/real 1073741824, 4065; load=0.500000
%load/real v0x5610fda77250_0;
%mul/wr;
%store/real v0x5610fda77180_0;
%pushi/real 1073741824, 4065; load=0.500000
%load/real v0x5610fda77250_0;
%mul/wr;
%store/real v0x5610fda770c0_0;
%load/real v0x5610fda77250_0;
%pushi/vec4 4, 0, 32;
%cvt/rv/s;
%div/wr;
%store/real v0x5610fda77400_0;
%load/real v0x5610fda77400_0;
%pushi/vec4 0, 0, 32;
%cvt/rv/s;
%mul/wr;
%pushi/vec4 90, 0, 32;
%cvt/rv/s;
%div/wr;
%store/real v0x5610fda77560_0;
%end;
.thread T_5, $init;
.scope S_0x5610fda76bd0;
T_6 ;
%vpi_call/w 4 18 "$display", "FREQ = %0d kHz", P_0x5610fda76df0 {0 0 0};
%vpi_call/w 4 19 "$display", "PHASE = %0d deg", P_0x5610fda76e30 {0 0 0};
%vpi_call/w 4 20 "$display", "DUTY = %0d %%", P_0x5610fda76db0 {0 0 0};
%vpi_call/w 4 22 "$display", "PERIOD = %0.1f ms", v0x5610fda77250_0 {0 0 0};
%vpi_call/w 4 23 "$display", "CLK_ON = %0.1f ms", v0x5610fda77180_0 {0 0 0};
%vpi_call/w 4 24 "$display", "CLK_OFF = %0.1f ms", v0x5610fda770c0_0 {0 0 0};
%vpi_call/w 4 25 "$display", "QUARTER = %0.1f ms", v0x5610fda77400_0 {0 0 0};
%vpi_call/w 4 26 "$display", "START_DLY = %0.1f ms", v0x5610fda77560_0 {0 0 0};
%end;
.thread T_6;
.scope S_0x5610fda76bd0;
T_7 ;
%pushi/vec4 0, 0, 1;
%assign/vec4 v0x5610fda76fe0_0, 0;
%pushi/vec4 0, 0, 1;
%assign/vec4 v0x5610fda774a0_0, 0;
%end;
.thread T_7;
.scope S_0x5610fda76bd0;
T_8 ;
%wait E_0x5610fda47160;
%load/vec4 v0x5610fda77310_0;
%flag_set/vec4 8;
%jmp/0xz T_8.0, 8;
%load/real v0x5610fda77560_0;
%pushi/real 2097152000, 4075; load=1000.00
%mul/wr;
%cvt/vr 64;
%muli 1, 0, 64;
%ix/vec4 4;
%delayx 4;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x5610fda774a0_0, 0, 1;
%jmp T_8.1;
T_8.0 ;
%load/real v0x5610fda77560_0;
%pushi/real 2097152000, 4075; load=1000.00
%mul/wr;
%cvt/vr 64;
%muli 1, 0, 64;
%ix/vec4 4;
%delayx 4;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x5610fda774a0_0, 0, 1;
T_8.1 ;
%jmp T_8;
.thread T_8;
.scope S_0x5610fda76bd0;
T_9 ;
%wait E_0x5610fda2f6d0;
%load/vec4 v0x5610fda774a0_0;
%flag_set/vec4 8;
%jmp/0xz T_9.0, 8;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x5610fda76fe0_0, 0, 1;
T_9.2 ;
%load/vec4 v0x5610fda774a0_0;
%flag_set/vec4 8;
%jmp/0xz T_9.3, 8;
%load/real v0x5610fda77180_0;
%pushi/real 2097152000, 4075; load=1000.00
%mul/wr;
%cvt/vr 64;
%muli 1, 0, 64;
%ix/vec4 4;
%delayx 4;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x5610fda76fe0_0, 0, 1;
%load/real v0x5610fda770c0_0;
%pushi/real 2097152000, 4075; load=1000.00
%mul/wr;
%cvt/vr 64;
%muli 1, 0, 64;
%ix/vec4 4;
%delayx 4;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x5610fda76fe0_0, 0, 1;
%jmp T_9.2;
T_9.3 ;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x5610fda76fe0_0, 0, 1;
T_9.0 ;
%jmp T_9;
.thread T_9;
.scope S_0x5610fda77680;
T_10 ;
%pushi/real 1342177280, 4068; load=5.00000
%store/real v0x5610fda77db0_0;
%pushi/real 1073741824, 4065; load=0.500000
%load/real v0x5610fda77db0_0;
%mul/wr;
%store/real v0x5610fda77ce0_0;
%pushi/real 1073741824, 4065; load=0.500000
%load/real v0x5610fda77db0_0;
%mul/wr;
%store/real v0x5610fda77c20_0;
%load/real v0x5610fda77db0_0;
%pushi/vec4 4, 0, 32;
%cvt/rv/s;
%div/wr;
%store/real v0x5610fda77fb0_0;
%load/real v0x5610fda77fb0_0;
%pushi/vec4 0, 0, 32;
%cvt/rv/s;
%mul/wr;
%pushi/vec4 90, 0, 32;
%cvt/rv/s;
%div/wr;
%store/real v0x5610fda78130_0;
%end;
.thread T_10, $init;
.scope S_0x5610fda77680;
T_11 ;
%vpi_call/w 4 18 "$display", "FREQ = %0d kHz", P_0x5610fda778d0 {0 0 0};
%vpi_call/w 4 19 "$display", "PHASE = %0d deg", P_0x5610fda77910 {0 0 0};
%vpi_call/w 4 20 "$display", "DUTY = %0d %%", P_0x5610fda77890 {0 0 0};
%vpi_call/w 4 22 "$display", "PERIOD = %0.1f ms", v0x5610fda77db0_0 {0 0 0};
%vpi_call/w 4 23 "$display", "CLK_ON = %0.1f ms", v0x5610fda77ce0_0 {0 0 0};
%vpi_call/w 4 24 "$display", "CLK_OFF = %0.1f ms", v0x5610fda77c20_0 {0 0 0};
%vpi_call/w 4 25 "$display", "QUARTER = %0.1f ms", v0x5610fda77fb0_0 {0 0 0};
%vpi_call/w 4 26 "$display", "START_DLY = %0.1f ms", v0x5610fda78130_0 {0 0 0};
%end;
.thread T_11;
.scope S_0x5610fda77680;
T_12 ;
%pushi/vec4 0, 0, 1;
%assign/vec4 v0x5610fda77b40_0, 0;
%pushi/vec4 0, 0, 1;
%assign/vec4 v0x5610fda78070_0, 0;
%end;
.thread T_12;
.scope S_0x5610fda77680;
T_13 ;
%wait E_0x5610fda47160;
%load/vec4 v0x5610fda77e70_0;
%flag_set/vec4 8;
%jmp/0xz T_13.0, 8;
%load/real v0x5610fda78130_0;
%pushi/real 2097152000, 4075; load=1000.00
%mul/wr;
%cvt/vr 64;
%muli 1, 0, 64;
%ix/vec4 4;
%delayx 4;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x5610fda78070_0, 0, 1;
%jmp T_13.1;
T_13.0 ;
%load/real v0x5610fda78130_0;
%pushi/real 2097152000, 4075; load=1000.00
%mul/wr;
%cvt/vr 64;
%muli 1, 0, 64;
%ix/vec4 4;
%delayx 4;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x5610fda78070_0, 0, 1;
T_13.1 ;
%jmp T_13;
.thread T_13;
.scope S_0x5610fda77680;
T_14 ;
%wait E_0x5610fda77ae0;
%load/vec4 v0x5610fda78070_0;
%flag_set/vec4 8;
%jmp/0xz T_14.0, 8;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x5610fda77b40_0, 0, 1;
T_14.2 ;
%load/vec4 v0x5610fda78070_0;
%flag_set/vec4 8;
%jmp/0xz T_14.3, 8;
%load/real v0x5610fda77ce0_0;
%pushi/real 2097152000, 4075; load=1000.00
%mul/wr;
%cvt/vr 64;
%muli 1, 0, 64;
%ix/vec4 4;
%delayx 4;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x5610fda77b40_0, 0, 1;
%load/real v0x5610fda77c20_0;
%pushi/real 2097152000, 4075; load=1000.00
%mul/wr;
%cvt/vr 64;
%muli 1, 0, 64;
%ix/vec4 4;
%delayx 4;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x5610fda77b40_0, 0, 1;
%jmp T_14.2;
T_14.3 ;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x5610fda77b40_0, 0, 1;
T_14.0 ;
%jmp T_14;
.thread T_14;
.scope S_0x5610fda78250;
T_15 ;
%pushi/real 1342177280, 4067; load=2.50000
%store/real v0x5610fda78950_0;
%pushi/real 1073741824, 4065; load=0.500000
%load/real v0x5610fda78950_0;
%mul/wr;
%store/real v0x5610fda78880_0;
%pushi/real 1073741824, 4065; load=0.500000
%load/real v0x5610fda78950_0;
%mul/wr;
%store/real v0x5610fda787c0_0;
%load/real v0x5610fda78950_0;
%pushi/vec4 4, 0, 32;
%cvt/rv/s;
%div/wr;
%store/real v0x5610fda78b00_0;
%load/real v0x5610fda78b00_0;
%pushi/vec4 0, 0, 32;
%cvt/rv/s;
%mul/wr;
%pushi/vec4 90, 0, 32;
%cvt/rv/s;
%div/wr;
%store/real v0x5610fda78c80_0;
%end;
.thread T_15, $init;
.scope S_0x5610fda78250;
T_16 ;
%vpi_call/w 4 18 "$display", "FREQ = %0d kHz", P_0x5610fda78470 {0 0 0};
%vpi_call/w 4 19 "$display", "PHASE = %0d deg", P_0x5610fda784b0 {0 0 0};
%vpi_call/w 4 20 "$display", "DUTY = %0d %%", P_0x5610fda78430 {0 0 0};
%vpi_call/w 4 22 "$display", "PERIOD = %0.1f ms", v0x5610fda78950_0 {0 0 0};
%vpi_call/w 4 23 "$display", "CLK_ON = %0.1f ms", v0x5610fda78880_0 {0 0 0};
%vpi_call/w 4 24 "$display", "CLK_OFF = %0.1f ms", v0x5610fda787c0_0 {0 0 0};
%vpi_call/w 4 25 "$display", "QUARTER = %0.1f ms", v0x5610fda78b00_0 {0 0 0};
%vpi_call/w 4 26 "$display", "START_DLY = %0.1f ms", v0x5610fda78c80_0 {0 0 0};
%end;
.thread T_16;
.scope S_0x5610fda78250;
T_17 ;
%pushi/vec4 0, 0, 1;
%assign/vec4 v0x5610fda786e0_0, 0;
%pushi/vec4 0, 0, 1;
%assign/vec4 v0x5610fda78bc0_0, 0;
%end;
.thread T_17;
.scope S_0x5610fda78250;
T_18 ;
%wait E_0x5610fda47160;
%load/vec4 v0x5610fda78a10_0;
%flag_set/vec4 8;
%jmp/0xz T_18.0, 8;
%load/real v0x5610fda78c80_0;
%pushi/real 2097152000, 4075; load=1000.00
%mul/wr;
%cvt/vr 64;
%muli 1, 0, 64;
%ix/vec4 4;
%delayx 4;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x5610fda78bc0_0, 0, 1;
%jmp T_18.1;
T_18.0 ;
%load/real v0x5610fda78c80_0;
%pushi/real 2097152000, 4075; load=1000.00
%mul/wr;
%cvt/vr 64;
%muli 1, 0, 64;
%ix/vec4 4;
%delayx 4;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x5610fda78bc0_0, 0, 1;
T_18.1 ;
%jmp T_18;
.thread T_18;
.scope S_0x5610fda78250;
T_19 ;
%wait E_0x5610fda78660;
%load/vec4 v0x5610fda78bc0_0;
%flag_set/vec4 8;
%jmp/0xz T_19.0, 8;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x5610fda786e0_0, 0, 1;
T_19.2 ;
%load/vec4 v0x5610fda78bc0_0;
%flag_set/vec4 8;
%jmp/0xz T_19.3, 8;
%load/real v0x5610fda78880_0;
%pushi/real 2097152000, 4075; load=1000.00
%mul/wr;
%cvt/vr 64;
%muli 1, 0, 64;
%ix/vec4 4;
%delayx 4;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x5610fda786e0_0, 0, 1;
%load/real v0x5610fda787c0_0;
%pushi/real 2097152000, 4075; load=1000.00
%mul/wr;
%cvt/vr 64;
%muli 1, 0, 64;
%ix/vec4 4;
%delayx 4;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x5610fda786e0_0, 0, 1;
%jmp T_19.2;
T_19.3 ;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x5610fda786e0_0, 0, 1;
T_19.0 ;
%jmp T_19;
.thread T_19;
.scope S_0x5610fda4b860;
T_20 ;
%vpi_call/w 3 15 "$dumpfile", "test.lx2" {0 0 0};
%vpi_call/w 3 16 "$dumpvars", 32'sb00000000000000000000000000000000, S_0x5610fda76bd0, S_0x5610fda77680, S_0x5610fda78250 {0 0 0};
%pushi/vec4 0, 0, 1;
%assign/vec4 v0x5610fda791d0_0, 0;
%pushi/vec4 0, 0, 32;
%store/vec4 v0x5610fda79270_0, 0, 32;
T_20.0 ;
%load/vec4 v0x5610fda79270_0;
%cmpi/s 10, 0, 32;
%jmp/0xz T_20.1, 5;
%vpi_func 3 20 "$random" 32 {0 0 0};
%pad/s 8;
%store/vec4 v0x5610fda790e0_0, 0, 8;
%load/vec4 v0x5610fda790e0_0;
%pad/u 64;
%muli 1000, 0, 64;
%ix/vec4 4;
%delayx 4;
%load/vec4 v0x5610fda791d0_0;
%inv;
%assign/vec4 v0x5610fda791d0_0, 0;
%vpi_call/w 3 22 "$display", "i=%0d delay=%0d", v0x5610fda79270_0, v0x5610fda790e0_0 {0 0 0};
%delay 50000, 0;
%load/vec4 v0x5610fda79270_0;
%addi 1, 0, 32;
%store/vec4 v0x5610fda79270_0, 0, 32;
%jmp T_20.0;
T_20.1 ;
%delay 50000, 0;
%vpi_call/w 3 26 "$finish" {0 0 0};
%end;
.thread T_20;
# The file index is used to find the file name in the following table.
:file_names 5;
"N/A";
"<interactive>";
"-";
"clock-tb.v";
"clock.v";