(Tim) Efthymios Kritikos a13ffe57b6 Fixed VPP typo. should be VVP		2023-02-07 17:55:57 +00:00
..
clock	Fixed VPP typo. should be VVP	2023-02-07 17:55:57 +00:00
counter	Fixed git ignore and cleanup	2023-02-06 21:09:55 +00:00
hello_world	Fixed git ignore and cleanup	2023-02-06 21:09:55 +00:00
multiplexer	Wrote my first verilog project ( a multiplexer ) with a testbench and added a .gitignore	2023-01-24 20:27:15 +00:00
VPI_example	Added clock and gtkwave integration	2023-02-07 17:52:02 +00:00