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be402aa8f7
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Project: updated copyright notices and README and fixed a few spelling mistakes
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2024-02-10 15:52:13 +00:00 |
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1d9be44c5a
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Build system: renamed upload to upload_bitstream to allow for an upload_firmware in the future
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2024-01-22 20:19:14 +00:00 |
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8fb6dadf48
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Documentation: Updated README.md with the improvements in gen_litedram.sh
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2023-12-04 22:32:21 +00:00 |
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63ea29e399
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Peripherals/Memory: Added support for the litedram DDR memory controller, created a new memory map and updated all relevant code and files including the addition of rudimentary wait state support for the cpu (BIU)
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2023-12-03 19:24:39 +00:00 |
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29bc2e6d96
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Project: Cleaned up some code and run the project through aspell
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2023-11-15 14:37:46 +00:00 |
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e0dc7bae07
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Move the diagram below some text since it looks a bit ugly this way
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2023-11-07 14:40:51 +00:00 |
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1a1634c673
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Updated README, improved fpga-specific makefile options and updated the version number
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2023-11-07 14:37:22 +00:00 |
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4767a7addc
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Updated progress on README
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2023-11-06 08:18:19 +00:00 |
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5feee9de57
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Added support to the build system for synthesising, place and routing, serialising and uploading the design to a Lattice ECP5 OrangeCrab FPGA
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2023-11-02 00:29:14 +00:00 |
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cfed0b4117
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Made the temporary logo a bit more centered. Also removed an incorrect line in README
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2023-10-24 01:08:13 +01:00 |
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8d3b54b812
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Small change from when I last worked on this and an update to the versions on the README
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2023-10-21 18:38:50 +01:00 |
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79d598fc64
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Changed slogan and cleaned up some small pieces of code
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2023-05-23 16:18:33 +01:00 |
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aca3357cda
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Fixed README formatting error
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2023-05-16 14:06:17 +01:00 |
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97912b1a29
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Fixed bug found by icarus verilog and added outdated notice to README
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2023-05-16 13:59:16 +01:00 |
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fe0426a77b
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Made execute unit run in parallel with everything else. Still not parallel for most of the time though
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2023-05-13 06:51:35 +01:00 |
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539fb8416b
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Fixed copyright notices, did some major cleanup and bumped README's versions
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2023-05-11 16:28:10 +01:00 |
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88a47cc4a9
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Slight change in REAMDE's wording
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2023-05-04 03:47:25 +01:00 |
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133bd33a9c
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Added definition of the version names to README
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2023-05-04 03:43:44 +01:00 |
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c25d2eaf19
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Added a high level state diagram of the processor
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2023-03-21 12:38:35 +00:00 |
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d93c92c005
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Slight adjustment to README
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2023-03-06 21:57:36 +00:00 |
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e8b84a38b6
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Updated README.md about verilator
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2023-03-05 06:37:07 +00:00 |
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e1bb98c0f0
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Updated toolchain versions and run project through aspell
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2023-03-03 06:54:33 +00:00 |
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e2e9a92832
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Cleaned the decoder a bit and laid down some of the groundwork for microcode
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2023-02-19 16:22:23 +00:00 |
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e6c9c722e3
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Run the project through aspell and tweaked the README
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2023-02-19 00:52:52 +00:00 |
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fd4a9b5442
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Fixed register addressing bug, mem read endianness, cleaned up code and added a provisional project logo
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2023-02-19 00:20:53 +00:00 |
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ded47555a5
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Improved build system and project directory structure
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2023-02-16 01:52:02 +00:00 |
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5e0c990394
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It is Turing complete! Running the Mandelbrot renderer with the brainfuck interpreter. Improved addressing modes and added CMP immediate with register instruction
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2023-02-15 03:54:12 +00:00 |
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7c1067088c
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Properly licensed the project and run it through aspell
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2023-02-13 16:49:17 +00:00 |
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d7eb4f36c0
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Wrote very basic brainfuck interpreter in 8086 asm to work on making it run and prove Turing completeness
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2023-02-11 01:12:54 +00:00 |
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57b159bce3
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Wrote a README
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2023-02-10 13:27:15 +00:00 |
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f94a0e9bb3
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Initial commit
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2023-02-08 08:38:10 +00:00 |
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