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f471b305d8
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Switched some assignments in decode.v to non-blocking which fixed a seemingly unrelated bug with incrementing the accumulator, added some more working test code in colored_led.asm and did some semantic changes as per yosys suggestions
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2023-11-12 02:54:41 +00:00 |
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4c130a8d63
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Added back removed warnings to verilator since we have now fixed those issues
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2023-11-12 00:07:33 +00:00 |
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09b3d51015
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Added statistics to place&route
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2023-11-09 23:10:06 +00:00 |
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a88c420ca5
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Added an I2C driver, a PCF8574 driver and an HD44780 display driver. Unfortunately this shows that even fibonacci doesn't run correctly. Nonetheless, I made colored_led.asm output text to the display!
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2023-11-09 22:10:55 +00:00 |
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1a1634c673
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Updated README, improved fpga-specific makefile options and updated the version number
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2023-11-07 14:37:22 +00:00 |
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01dcbfa7a1
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The CPU works on real hardware for the first time! I added an adjustment for ram size, added control for a led and a test program for it. On the fpga board there is an actual led there that I used to verify functionality
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2023-11-06 08:13:36 +00:00 |
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30ffa1b00c
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Fixed a "combinatorial loop" and now if the build-in memory is reduced the design can be synthesized!
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2023-11-06 05:36:04 +00:00 |
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5ebd53b11c
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fixed more driver conflicts
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2023-11-06 01:35:48 +00:00 |
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ae16c79b0a
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Fixed another driver conflict
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2023-11-05 20:18:11 +00:00 |
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9947517693
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Fixed simulation with icarus verilog and removed another driver conflict
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2023-11-05 19:43:49 +00:00 |
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4a5df9c74e
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Fixed another driver conflict
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2023-11-05 16:23:05 +00:00 |
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aa9b7c0a50
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Removed more "conflicting driver" issues with yet more performance penalties...
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2023-11-04 15:33:23 +00:00 |
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df2975fa09
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Fixed a lot of "conflicting driver" issues but I had to roll back an optimisation
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2023-11-04 11:04:22 +00:00 |
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c7ddf3fa9e
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More small fixes
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2023-11-04 08:31:05 +00:00 |
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694f708a32
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Fixed some relatively low hanging fruit
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2023-11-04 08:08:22 +00:00 |
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934e2f5a36
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Fixed a bunch of things wrong with fpga_top.v and gated off some more simulation-only code
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2023-11-02 23:46:12 +00:00 |
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08aac5c7b6
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Removed some code that wasn't meant for synthesis and fixed important bug in Makefile
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2023-11-02 22:19:15 +00:00 |
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601397b7f0
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Properly added fpga_top.v stuff in the build system and fixed some syntax errors
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2023-11-02 22:00:07 +00:00 |
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43f3e16ca4
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Removed all instances of inout since from what i understand it's mostly synthesisable
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2023-11-02 21:48:12 +00:00 |
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36bf8f9c7a
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Added OrangeCrab board-specific code to connect the cpu to the outside world
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2023-11-02 20:40:04 +00:00 |
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5feee9de57
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Added support to the build system for synthesising, place and routing, serialising and uploading the design to a Lattice ECP5 OrangeCrab FPGA
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2023-11-02 00:29:14 +00:00 |
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85512d5ace
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Last minute fix of dependencies in Makefile before release
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2023-11-01 19:09:59 +00:00 |
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3ec90b1843
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Added version stamp and last commit to json log
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2023-11-01 06:03:53 +00:00 |
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557d160be6
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did some cleanup relating to the generation of the VALID_INSTRUCTION signal
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2023-11-01 05:00:09 +00:00 |
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3a63e916f5
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Added cycles to waveform capture for icarus verilog
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2023-10-31 19:32:35 +00:00 |
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49335a2c2f
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Fixed a small bug in log generation and did some cleanup
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2023-10-31 19:01:34 +00:00 |
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8a62b89a13
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Fixed small bug with json data reporting and improved slightly the graphs
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2023-10-30 08:01:03 +00:00 |
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d151435ac1
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Removed redundant checks for enabled early instruction detection in BIU
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2023-10-23 02:30:25 +01:00 |
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ced03c48d6
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Added cache flush after write, potentially fixing support for self modifying code
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2023-10-23 02:09:13 +01:00 |
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8d3b54b812
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Small change from when I last worked on this and an update to the versions on the README
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2023-10-21 18:38:50 +01:00 |
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42c319d55d
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Lots of cleanup mainly on processor.v
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2023-06-01 02:13:55 +01:00 |
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a693b87e96
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General cleanup and moved the reading of instruction parameters from a separate stage in execute to circuitry during the decode
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2023-05-29 02:29:15 +01:00 |
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af63ef1d68
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Moved the decoder logic to decoder.v Now processor.v only connects the different modules
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2023-05-27 23:35:00 +01:00 |
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d2a98c02ff
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Removed duplicate code and improved microcode entry
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2023-05-27 17:59:52 +01:00 |
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79d598fc64
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Changed slogan and cleaned up some small pieces of code
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2023-05-23 16:18:33 +01:00 |
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0bf00df07c
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Fixed clock cycle and instruction counter overflow
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2023-05-23 09:27:46 +01:00 |
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e74d73ed58
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Added reporting of branches on the stat json files and improved the plotting script
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2023-05-21 03:00:27 +01:00 |
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3dd2ff59ea
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Added 2 more test programs, 2 new instructions and fixed a bug in CMP
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2023-05-21 01:48:50 +01:00 |
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021dd06e9a
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Added support for some more instructions, fixed a bug in CMP and also added a program that uses them
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2023-05-19 17:59:20 +01:00 |
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1b510e4781
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Made the size of the cache variable
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2023-05-18 11:21:27 +01:00 |
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7db70d79ff
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Made execute unit start at a state transition of a signal from the decoder thus allowing for an IPC of 0.99 !!
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2023-05-17 21:30:21 +01:00 |
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90f63b525d
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Made the decode unit able to continuously decode (simple) instructions if BIU allows it
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2023-05-17 20:09:38 +01:00 |
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30c3deca37
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Made the execute unit signal the end of execution by a state change rather than the state of a signal to allow for one cycle instructions
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2023-05-17 11:05:20 +01:00 |
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53e9d371d7
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Fully optimised BIU. Now it can instantly deliver instructions back to back
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2023-05-16 18:07:28 +01:00 |
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f914d1ec8f
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Cleaned up processor.v a bit
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2023-05-16 16:29:48 +01:00 |
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97912b1a29
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Fixed bug found by icarus verilog and added outdated notice to README
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2023-05-16 13:59:16 +01:00 |
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bfa576e2a0
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Cleaned up the interface between BIU and the processor
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2023-05-16 13:33:08 +01:00 |
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07d2a80b2e
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Added code to record statistics and a tool to plot them
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2023-05-14 16:06:33 +01:00 |
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df342467c7
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Saved a clock cycle from microcode starts and added info in decode to allow saving a cycle on almost every instruction
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2023-05-13 13:45:15 +01:00 |
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00aa828ddc
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Improved parallelism
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2023-05-13 10:52:44 +01:00 |
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