|
|
9947517693
|
Fixed simulation with icarus verilog and removed another driver conflict
|
2023-11-05 19:43:49 +00:00 |
|
|
|
4a5df9c74e
|
Fixed another driver conflict
|
2023-11-05 16:23:05 +00:00 |
|
|
|
aa9b7c0a50
|
Removed more "conflicting driver" issues with yet more performance penalties...
|
2023-11-04 15:33:23 +00:00 |
|
|
|
df2975fa09
|
Fixed a lot of "conflicting driver" issues but I had to roll back an optimisation
|
2023-11-04 11:04:22 +00:00 |
|
|
|
c7ddf3fa9e
|
More small fixes
|
2023-11-04 08:31:05 +00:00 |
|
|
|
694f708a32
|
Fixed some relatively low hanging fruit
|
2023-11-04 08:08:22 +00:00 |
|
|
|
934e2f5a36
|
Fixed a bunch of things wrong with fpga_top.v and gated off some more simulation-only code
|
2023-11-02 23:46:12 +00:00 |
|
|
|
08aac5c7b6
|
Removed some code that wasn't meant for synthesis and fixed important bug in Makefile
|
2023-11-02 22:19:15 +00:00 |
|
|
|
601397b7f0
|
Properly added fpga_top.v stuff in the build system and fixed some syntax errors
|
2023-11-02 22:00:07 +00:00 |
|
|
|
43f3e16ca4
|
Removed all instances of inout since from what i understand it's mostly synthesisable
|
2023-11-02 21:48:12 +00:00 |
|
|
|
36bf8f9c7a
|
Added OrangeCrab board-specific code to connect the cpu to the outside world
|
2023-11-02 20:40:04 +00:00 |
|
|
|
5feee9de57
|
Added support to the build system for synthesising, place and routing, serialising and uploading the design to a Lattice ECP5 OrangeCrab FPGA
|
2023-11-02 00:29:14 +00:00 |
|
|
|
85512d5ace
|
Last minute fix of dependencies in Makefile before release
|
2023-11-01 19:09:59 +00:00 |
|
|
|
3ec90b1843
|
Added version stamp and last commit to json log
|
2023-11-01 06:03:53 +00:00 |
|
|
|
557d160be6
|
did some cleanup relating to the generation of the VALID_INSTRUCTION signal
|
2023-11-01 05:00:09 +00:00 |
|
|
|
3a63e916f5
|
Added cycles to waveform capture for icarus verilog
|
2023-10-31 19:32:35 +00:00 |
|
|
|
49335a2c2f
|
Fixed a small bug in log generation and did some cleanup
|
2023-10-31 19:01:34 +00:00 |
|
|
|
8a62b89a13
|
Fixed small bug with json data reporting and improved slightly the graphs
|
2023-10-30 08:01:03 +00:00 |
|
|
|
d151435ac1
|
Removed redundant checks for enabled early instruction detection in BIU
|
2023-10-23 02:30:25 +01:00 |
|
|
|
ced03c48d6
|
Added cache flush after write, potentially fixing support for self modifying code
|
2023-10-23 02:09:13 +01:00 |
|
|
|
8d3b54b812
|
Small change from when I last worked on this and an update to the versions on the README
|
2023-10-21 18:38:50 +01:00 |
|
|
|
42c319d55d
|
Lots of cleanup mainly on processor.v
|
2023-06-01 02:13:55 +01:00 |
|
|
|
a693b87e96
|
General cleanup and moved the reading of instruction parameters from a separate stage in execute to circuitry during the decode
|
2023-05-29 02:29:15 +01:00 |
|
|
|
af63ef1d68
|
Moved the decoder logic to decoder.v Now processor.v only connects the different modules
|
2023-05-27 23:35:00 +01:00 |
|
|
|
d2a98c02ff
|
Removed duplicate code and improved microcode entry
|
2023-05-27 17:59:52 +01:00 |
|
|
|
79d598fc64
|
Changed slogan and cleaned up some small pieces of code
|
2023-05-23 16:18:33 +01:00 |
|
|
|
0bf00df07c
|
Fixed clock cycle and instruction counter overflow
|
2023-05-23 09:27:46 +01:00 |
|
|
|
e74d73ed58
|
Added reporting of branches on the stat json files and improved the plotting script
|
2023-05-21 03:00:27 +01:00 |
|
|
|
3dd2ff59ea
|
Added 2 more test programs, 2 new instructions and fixed a bug in CMP
|
2023-05-21 01:48:50 +01:00 |
|
|
|
021dd06e9a
|
Added support for some more instructions, fixed a bug in CMP and also added a program that uses them
|
2023-05-19 17:59:20 +01:00 |
|
|
|
1b510e4781
|
Made the size of the cache variable
|
2023-05-18 11:21:27 +01:00 |
|
|
|
7db70d79ff
|
Made execute unit start at a state transition of a signal from the decoder thus allowing for an IPC of 0.99 !!
|
2023-05-17 21:30:21 +01:00 |
|
|
|
90f63b525d
|
Made the decode unit able to continuously decode (simple) instructions if BIU allows it
|
2023-05-17 20:09:38 +01:00 |
|
|
|
30c3deca37
|
Made the execute unit signal the end of execution by a state change rather than the state of a signal to allow for one cycle instructions
|
2023-05-17 11:05:20 +01:00 |
|
|
|
53e9d371d7
|
Fully optimised BIU. Now it can instantly deliver instructions back to back
|
2023-05-16 18:07:28 +01:00 |
|
|
|
f914d1ec8f
|
Cleaned up processor.v a bit
|
2023-05-16 16:29:48 +01:00 |
|
|
|
97912b1a29
|
Fixed bug found by icarus verilog and added outdated notice to README
|
2023-05-16 13:59:16 +01:00 |
|
|
|
bfa576e2a0
|
Cleaned up the interface between BIU and the processor
|
2023-05-16 13:33:08 +01:00 |
|
|
|
07d2a80b2e
|
Added code to record statistics and a tool to plot them
|
2023-05-14 16:06:33 +01:00 |
|
|
|
df342467c7
|
Saved a clock cycle from microcode starts and added info in decode to allow saving a cycle on almost every instruction
|
2023-05-13 13:45:15 +01:00 |
|
|
|
00aa828ddc
|
Improved parallelism
|
2023-05-13 10:52:44 +01:00 |
|
|
|
fe0426a77b
|
Made execute unit run in parallel with everything else. Still not parallel for most of the time though
|
2023-05-13 06:51:35 +01:00 |
|
|
|
7151d5634f
|
Fixed bug that prevented Icarus Verilog from simulating correctly
|
2023-05-11 19:55:47 +01:00 |
|
|
|
539fb8416b
|
Fixed copyright notices, did some major cleanup and bumped README's versions
|
2023-05-11 16:28:10 +01:00 |
|
|
|
a8ab6b2dc7
|
Separated the execution unit from decode
|
2023-05-11 12:22:49 +01:00 |
|
|
|
7724e5f383
|
Removed deprecated BIU_NEXT_POSITION
|
2023-05-10 08:53:29 +01:00 |
|
|
|
e4ef199b83
|
Fixed a memory corruption bug
|
2023-05-10 08:35:14 +01:00 |
|
|
|
7e612bb701
|
made BIU snoop into the processor to deliver new instructions faster and fixed some bugs
|
2023-05-10 08:31:14 +01:00 |
|
|
|
c854818d6d
|
Tightened up write timing
|
2023-05-10 04:43:09 +01:00 |
|
|
|
b7bfbd4e33
|
Improved BIU performance and debug messages
|
2023-05-10 04:05:56 +01:00 |
|
