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3e66336456
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Build system: Small fixes and corrected rebuild when only the verilator testbench was changed
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2023-12-09 02:39:14 +00:00 |
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94bc6eba39
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Build system: Added help text and target mrproper which also deletes downloaded source code
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2023-12-08 22:10:11 +00:00 |
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533f346f9b
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Build system: Added the ability to simulate an FPGA SoC and fixed all the warning verilator gave of the code previously used only for synthesis.
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2023-12-07 16:39:04 +00:00 |
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b1108e375d
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Build system: Fixed standalone ./system/Makefile build and general Makefile improvements
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2023-12-06 18:13:24 +00:00 |
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8edafd70cf
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Build system: Improved the handling of seeds, moved most of the board specific build instructions to the board specific .mk file and fixed bios.asm dependencies
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2023-12-05 21:46:56 +00:00 |
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dd1080b42c
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Build system: Added maximum CPU frequency to build system info and improved the way nextpnr seed is handled, fixing builds with older versions of make
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2023-12-05 01:13:43 +00:00 |
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0eecfdcf40
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Tools/Gen_litedram: Major improvements and cleanup including work in ensuring it is reproducible
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2023-12-04 21:36:48 +00:00 |
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63ea29e399
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Peripherals/Memory: Added support for the litedram DDR memory controller, created a new memory map and updated all relevant code and files including the addition of rudimentary wait state support for the cpu (BIU)
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2023-12-03 19:24:39 +00:00 |
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17638d5cbd
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Build system: Slight improvements, randomised nextpnr rng seed and printed it to the terminal. In case timing fails running it a bunch of times can yield one value that passes.
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2023-11-23 23:27:19 +00:00 |
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aedefddb5d
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Project: The cpu finally works perfectly now even at full speed as far as i can tell! I made the ram and register writes synchronous which fixed the weird issues I had, then I added -abc9 to yosys so that nextpnr can actually route the cpu at full speed and increased the display fifo since the cpu is so fast now!!
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2023-11-15 18:43:56 +00:00 |
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29bc2e6d96
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Project: Cleaned up some code and run the project through aspell
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2023-11-15 14:37:46 +00:00 |
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2c8e8a9d9c
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Added simple support for \n and \r on the HD44780 driver, increased the synthesised mem to fit brainfuck_compiled.asm and made it the default.
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2023-11-12 21:39:27 +00:00 |
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618c3102d8
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Fixed some dependencies on the makefiles
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2023-11-12 13:30:12 +00:00 |
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e06c0eeaa0
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Made the build system simplify the microcode so that yosys understands and synthesises it! Now gnome_sort.asm almost works!
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2023-11-12 04:04:56 +00:00 |
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4c130a8d63
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Added back removed warnings to verilator since we have now fixed those issues
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2023-11-12 00:07:33 +00:00 |
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09b3d51015
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Added statistics to place&route
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2023-11-09 23:10:06 +00:00 |
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a88c420ca5
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Added an I2C driver, a PCF8574 driver and an HD44780 display driver. Unfortunately this shows that even fibonacci doesn't run correctly. Nonetheless, I made colored_led.asm output text to the display!
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2023-11-09 22:10:55 +00:00 |
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1a1634c673
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Updated README, improved fpga-specific makefile options and updated the version number
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2023-11-07 14:37:22 +00:00 |
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01dcbfa7a1
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The CPU works on real hardware for the first time! I added an adjustment for ram size, added control for a led and a test program for it. On the fpga board there is an actual led there that I used to verify functionality
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2023-11-06 08:13:36 +00:00 |
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08aac5c7b6
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Removed some code that wasn't meant for synthesis and fixed important bug in Makefile
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2023-11-02 22:19:15 +00:00 |
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601397b7f0
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Properly added fpga_top.v stuff in the build system and fixed some syntax errors
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2023-11-02 22:00:07 +00:00 |
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36bf8f9c7a
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Added OrangeCrab board-specific code to connect the cpu to the outside world
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2023-11-02 20:40:04 +00:00 |
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5feee9de57
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Added support to the build system for synthesising, place and routing, serialising and uploading the design to a Lattice ECP5 OrangeCrab FPGA
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2023-11-02 00:29:14 +00:00 |
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85512d5ace
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Last minute fix of dependencies in Makefile before release
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2023-11-01 19:09:59 +00:00 |
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07d2a80b2e
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Added code to record statistics and a tool to plot them
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2023-05-14 16:06:33 +01:00 |
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a8ab6b2dc7
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Separated the execution unit from decode
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2023-05-11 12:22:49 +01:00 |
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da51dd6da7
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First draft of a bus interface unit in an effort to make the CPU pipelined. Currently supports code prefetching
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2023-05-07 13:34:15 +01:00 |
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8070d4e58a
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Improved build system's handling of verilator
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2023-03-05 23:11:18 +00:00 |
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99cbc49e95
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Wrote a more complete testbench for verilator, switched from lx2 to fst and fixed cpu clock frequency calculation
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2023-03-05 00:10:55 +00:00 |
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5705b8e8a5
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Added support for Verilator!
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2023-03-04 08:37:43 +00:00 |
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cac01f0333
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Fixed Makefile bug
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2023-02-22 01:51:14 +00:00 |
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7fde422341
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Added Microcode support, Stack, implemented the CALL instruction in microcode and grouped the wires on the decoder module
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2023-02-22 01:28:23 +00:00 |
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e2e9a92832
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Cleaned the decoder a bit and laid down some of the groundwork for microcode
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2023-02-19 16:22:23 +00:00 |
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fd4a9b5442
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Fixed register addressing bug, mem read endianness, cleaned up code and added a provisional project logo
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2023-02-19 00:20:53 +00:00 |
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82bd859874
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Moved the decoding of opcodes into a separate module and optimised memory reads
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2023-02-17 18:08:09 +00:00 |
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ed3d7101d3
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Further improved build system and changed brainfuck print message
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2023-02-16 23:26:32 +00:00 |
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ded47555a5
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Improved build system and project directory structure
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2023-02-16 01:52:02 +00:00 |
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