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7c1067088c
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Properly licensed the project and run it through aspell
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2023-02-13 16:49:17 +00:00 |
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0d4221f9de
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Added config file (mainly for debug verbosity) and kind of patched some weird behaviour when clock is stopped
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2023-02-13 15:24:21 +00:00 |
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16e02e0788
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Added conditional jump support!
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2023-02-13 10:36:37 +00:00 |
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923bf07c72
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Fixed ALU bug and added missed updates to the Wbit
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2023-02-12 01:28:37 +00:00 |
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c684348e38
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Implemented a CMP instruction and the some of the flags
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2023-02-12 01:05:39 +00:00 |
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0901af23db
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Added support for some register indirect addressing modes. Also added documentation comments and did some general cleanup
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2023-02-11 20:27:28 +00:00 |
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85bf886223
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Improved ALU and added more INC and a DEC instruction
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2023-02-11 14:43:53 +00:00 |
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be06244021
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Improved register file addressing and printout
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2023-02-11 13:41:12 +00:00 |
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fd31eb704c
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Made the simulation stop at an unrecognised instruction or other error
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2023-02-11 01:05:19 +00:00 |
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fc4ecdb8d2
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Added HLT instruction, made testbench count total clock cycles and write memdump and fixed reset timing
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2023-02-10 18:21:19 +00:00 |
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bba230fbce
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Added the MOV immediate to register instruction
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2023-02-10 15:41:04 +00:00 |
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e685c52ddd
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Improved instruction decoding
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2023-02-10 14:39:34 +00:00 |
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6561018206
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Made the processor actually little-endian
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2023-02-10 14:09:08 +00:00 |
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39f55aa6c3
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Added unaligned access for instructions and data and fixed register file access
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2023-02-10 12:02:20 +00:00 |
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185efe9d85
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Improved execution state logic, cleaned up code and fixed register file output enable
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2023-02-10 01:45:27 +00:00 |
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a5571fda12
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Added a very basic execution stage, registers and a very crude adder for ALU. It finally executes instructions!
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2023-02-09 20:17:15 +00:00 |
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a166efec9c
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Moved clock generator to the testbench
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2023-02-09 14:51:50 +00:00 |
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c3a2f5eb01
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Added primitive decode stage, improved state handling and fixed CIR register
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2023-02-09 14:46:21 +00:00 |
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5371caa3bb
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Implemented a basic Instruction Fetch stage and added some examples in the 8086 doc
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2023-02-08 23:59:06 +00:00 |
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139ec3c0c0
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Standardised indentation
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2023-02-08 12:09:21 +00:00 |
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61a403271c
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Added ROM, address and data buses and primitive program counter
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2023-02-08 11:57:22 +00:00 |
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bc2ef977d8
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Improved state logic
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2023-02-08 09:36:32 +00:00 |
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f9393cb69f
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Basic start for the control block
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2023-02-08 09:18:00 +00:00 |
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