298 lines
6.6 KiB
Verilog
298 lines
6.6 KiB
Verilog
`include "proc_state_def.v"
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module mux4 (in1,in2,in3,in4, sel,out);
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input [0:1] sel;
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parameter WIDTH=16;
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input [WIDTH-1:0] in1,in2,in3,in4;
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output [WIDTH-1:0] out;
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assign out = (sel == 'b00) ? in1 :
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(sel == 'b01) ? in2 :
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(sel == 'b10) ? in3 :
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in4;
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endmodule
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module processor ( input clock, input reset, output reg [19:0] external_address_bus, inout [15:0] external_data_bus,output reg read, output reg write, output reg HALT,output reg ERROR);
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/*** Global Definitions ***/
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// State
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reg [3:0] state;
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// Registers
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reg [19:0] ProgCount;
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reg [15:0] CIR;
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reg [15:0] PARAM1;
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reg [15:0] PARAM2;
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reg unaligned_access;
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// Execution units
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reg [1:0] in1_sel;
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reg [1:0] in2_sel;
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reg [1:0] out_sel;
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/*** RESET LOGIC ***/
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always @(negedge reset) begin
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if (reset==0) begin
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@(posedge clock);
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state=`PROC_HALT_STATE;
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ProgCount=0;//TODO: Reset Vector
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HALT=0;
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reg_write_we=1;
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reg_read_oe=1;
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unaligned_access=0;
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ALU_OUT=1;
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@(posedge reset)
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@(negedge clock);
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state=`PROC_IF_STATE_ENTRY;
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end
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end
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/*** ALU and EXEC stage logic ***/
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//Architectural Register file
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reg [3:0] reg_write_addr;
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reg [15:0] reg_write_data;
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reg reg_write_we;
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reg [3:0] reg_read_addr;
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reg [15:0] reg_read_data;
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reg reg_read_oe;
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register_file register_file(reg_write_addr,reg_write_data,reg_write_we,reg_read_addr,reg_read_data,reg_read_oe);
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//ALU
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mux4 #(.WIDTH(16)) MUX16_1A(
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PARAM1,
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16'b0,
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16'b0,
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16'b0,
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in1_sel,
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ADDER16_1A);
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mux4 #(.WIDTH(16)) MUX16_1B(
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PARAM2,
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reg_read_data,
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16'b0,
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16'b0,
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in2_sel,
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ADDER16_1B);
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wire [15:0] ADDER16_1A;
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wire [15:0] ADDER16_1B;
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wire [15:0] ADDER16_1O;
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wire ADDER16_1C;
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reg ALU_OUT;
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reg [15:0] temp_out;
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ADDER16 ADDER16_1(ADDER16_1A,ADDER16_1B,ALU_OUT,ADDER16_1O,ADDER16_1C);
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/*** Processor stages ***/
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`define invalid_instruction state=`PROC_IF_STATE_ENTRY;ERROR=1;
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always @(negedge clock) begin
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case(state)
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`PROC_IF_WRITE_CIR:begin
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if(unaligned_access)begin
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CIR[15:8] <= external_data_bus[7:0];
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ProgCount=ProgCount+1;
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state=`PROC_IF_STATE_EXTRA_FETCH_SET;
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end else begin
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CIR <= external_data_bus;
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state=`PROC_DE_STATE_ENTRY;
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end
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end
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`PROC_IF_STATE_EXTRA_FETCH:begin
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CIR[7:0] <= external_data_bus[15:8];
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state=`PROC_DE_STATE_ENTRY;
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end
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`PROC_EX_STATE_EXIT:begin
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case(out_sel)
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2'b11:begin
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reg_write_we=0;
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state=`PROC_IF_STATE_ENTRY;
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end
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default:begin
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`invalid_instruction
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end
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endcase
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end
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`PROC_DE_LOAD_16_EXTRA_FETCH_SET:begin
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external_address_bus = ProgCount;
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state=`PROC_DE_LOAD_16_EXTRA_FETCH;
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end
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endcase
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end
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always @(posedge clock) begin
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case(state)
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`PROC_HALT_STATE:begin
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end
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`PROC_IF_STATE_ENTRY:begin
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ERROR=0;
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external_address_bus <= ProgCount;
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read <= 0;
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write <= 1;
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reg_read_oe=1;
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reg_write_we=1;
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ALU_OUT=1;
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state=`PROC_IF_WRITE_CIR;
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end
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`PROC_IF_STATE_EXTRA_FETCH_SET:begin
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external_address_bus <= ProgCount;
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state=`PROC_IF_STATE_EXTRA_FETCH;
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end
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/* AFTER THE IF STAGE WE HAVE THE FRIST BYTE OF THE
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* INSTRUCTION ADN THE ONE FOLLOWING, ALLIGNED CORRECTLY TO
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* CIR */
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`PROC_DE_STATE_ENTRY:begin
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case(CIR[15:10])
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6'b000001 : begin
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/* ADD, ... */
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if ( CIR[9:9] == 0 )begin
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/* Add Immediate word/byte to accumulator */
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unaligned_access=~unaligned_access;
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in1_sel=2'b00;
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in2_sel=2'b01;
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out_sel=2'b11;
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reg_read_addr={CIR[8:8],3'b000};
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reg_write_addr={CIR[8:8],3'b000};
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reg_read_oe=0;
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ALU_OUT=0;
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if(CIR[8:8]==1)
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state=`PROC_DE_LOAD_16_PARAM;
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else begin
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`invalid_instruction /*do 8bit loads*/
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end
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end else begin
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`invalid_instruction
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end
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end
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6'b100000 : begin
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/* ADD, ADC, SUB, SBB, CMP , AND, ... */
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case (CIR[5:3])
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3'b000 : begin
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/* Add Immediate word/byte to register/memory */
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if(unaligned_access==0)begin
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ProgCount=ProgCount+1;
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external_address_bus <= ProgCount;
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end
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in1_sel=2'b00;
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in2_sel=2'b01;
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out_sel=CIR[7:6];
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reg_read_addr={CIR[8:8],CIR[2:0]};
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reg_write_addr={CIR[8:8],CIR[2:0]};
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reg_read_oe=0;
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ALU_OUT=0;
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state=`PROC_DE_LOAD_16_PARAM;
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if(CIR[8:8]==1)
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state=`PROC_DE_LOAD_16_PARAM;
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else begin
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`invalid_instruction /*do 8bit loads*/
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end
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end
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default:begin
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`invalid_instruction
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end
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endcase
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end
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6'b101100,
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6'b101101:begin
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/*Move Immediate byte to register*/
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if(unaligned_access==0)begin
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ProgCount=ProgCount+1;
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external_address_bus <= ProgCount;
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end
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unaligned_access=~unaligned_access;
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in1_sel=2'b00;
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in2_sel=2'b00;
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out_sel=2'b11;
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reg_write_addr={1'b0,CIR[10:8]};
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PARAM1[7:0]=CIR[7:0];
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PARAM2=0;
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ALU_OUT=0;
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state=`PROC_EX_STATE_ENTRY;
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end
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6'b101110,
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6'b101111 : begin
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/*Move Immediate word to register*/
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unaligned_access=~unaligned_access;
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in1_sel=2'b00;
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in2_sel=2'b00;
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out_sel=2'b11;
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reg_write_addr={1'b1,CIR[10:8]};
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ALU_OUT=0;
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PARAM2=0;
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state=`PROC_DE_LOAD_16_PARAM;
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end
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6'b111111 : begin
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/* INC */
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if (CIR[9:9] == 1 ) begin
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case (CIR[5:3])
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3'b000 :begin
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/* Increment Register or Memmory */
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if(unaligned_access==0)begin
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ProgCount=ProgCount+1;
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external_address_bus <= ProgCount;
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end
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in1_sel=2'b00;
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in2_sel=2'b01;
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out_sel=CIR[7:6];
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PARAM1=1;
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reg_read_addr={1'b0,CIR[2:0]};
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reg_write_addr={1'b0,CIR[2:0]};
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reg_read_oe=0;
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ALU_OUT=0;
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state=`PROC_EX_STATE_ENTRY;
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end
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default:begin
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`invalid_instruction
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end
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endcase
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end else begin
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`invalid_instruction
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end
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end
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6'b111101 : begin
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/*HLT, CMC, TEST, NOT, NEG, MUL, IMUL, .... */
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case (CIR[9:8])
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2'b00:begin
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/* HLT*/
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unaligned_access=~unaligned_access;
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HALT=1;
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state=`PROC_HALT_STATE;
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end
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default:begin
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`invalid_instruction;
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end
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endcase
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end
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default:begin
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`invalid_instruction
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end
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endcase
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end
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`PROC_DE_LOAD_16_PARAM:begin
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if(unaligned_access==1)begin
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PARAM1[7:0] = external_data_bus[7:0];
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ProgCount=ProgCount+1;
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state=`PROC_DE_LOAD_16_EXTRA_FETCH_SET;
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end else begin
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PARAM1[7:0] = external_data_bus[15:8];
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PARAM1[15:8] = external_data_bus[7:0];
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ProgCount=ProgCount+1;
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state=`PROC_EX_STATE_ENTRY;
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end
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end
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`PROC_DE_LOAD_16_EXTRA_FETCH:begin
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PARAM1[15:8] = external_data_bus[15:8];
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state=`PROC_EX_STATE_ENTRY;
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end
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`PROC_EX_STATE_ENTRY:begin
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reg_write_data=ADDER16_1O;
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state=`PROC_EX_STATE_EXIT;
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ERROR=0;
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end
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endcase
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end
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endmodule
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