158 lines
3.7 KiB
Verilog
158 lines
3.7 KiB
Verilog
`include "proc_state_def.v"
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module exec_units ( input [15:0]PARAM1, input [15:0]PARAM2, input [1:0]in1_sel, input [1:0]in2_sel, input [1:0]out_sel , input EXEC);
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/*Architectural Register file*/
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wire [2:0] reg_addr;
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wire [15:0] reg_data;
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wire reg_read;
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wire reg_write;
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wire [2:0] reg_read_addr;
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wire [15:0] reg_read_data;
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wire reg_read_read;
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register_file register_file(reg_addr,reg_data,reg_read,reg_write,reg_read_addr,reg_read_data,reg_read_read);
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/*Exec Unts*/
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wire [15:0] ADDER16_1A;
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wire [15:0] ADDER16_1B;
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wire [15:0] ADDER16_1O;
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wire ADDER16_1C;
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ADDER16 ADDER16_1(ADDER16_1A,ADDER16_1B,EXEC,ADDER16_1O,ADDER16_1C);
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/*logic*/
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assign reg_addr=PARAM2[5:3];
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assign reg_read=EXEC;
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assign reg_write=EXEC;
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assign reg_read_read=0;
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assign reg_read_addr=PARAM2[2:0];
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assign ADDER16_1A= (in1_sel==2'b00) ? PARAM1 : 16'b1010101010101010;
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assign ADDER16_1B= (in2_sel==2'b01) ? reg_read_data : 16'b1010101010101010;
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//assign reg_data = (out_sel==2'b01) ? ADDER16_1O : 'hz;
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//assign reg_data = (out_sel==2'b01) ? ADDER16_1O : ADDER16_1O;
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assign reg_data = ADDER16_1O;
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endmodule
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module processor ( input clock, input reset , output reg [19:0] external_address_bus, inout [15:0] external_data_bus,output reg read, output reg write, output reg HALT);
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/* State */
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reg [3:0] state;
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reg instruction_finished;
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/* Registers */
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reg [19:0] ProgCount;
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reg [15:0] CIR;
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reg [15:0] PARAM1;
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reg [15:0] PARAM2;
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/* Execution units*/
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reg [1:0] in1_sel;
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reg [1:0] in2_sel;
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reg [1:0] out_sel;
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reg exec_unit_execute;
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exec_units exec_units(PARAM1,PARAM2,in1_sel,in2_sel,out_sel,exec_unit_execute);
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/* RESET LOGIC */
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always @(negedge reset) begin
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if (reset==0) begin
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@(posedge clock);
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ProgCount=0;//TODO: Reset Vector
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EXCEPTION=0;
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HALT=0;
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exec_unit_execute=1;
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@(negedge clock);
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@(posedge clock);
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state=`PROC_IF_STATE_ENTRY;
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end
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end
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reg EXCEPTION;
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/* Processor stages */
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always @(negedge clock) begin
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case(state)
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`PROC_IF_WRITE_CIR:begin
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CIR <= external_data_bus;
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ProgCount=ProgCount+1;
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state=`PROC_DE_STATE_ENTRY;
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end
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`PROC_EX_STATE_EXIT:begin
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exec_unit_execute=1;
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state=`PROC_IF_STATE_ENTRY;
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end
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endcase
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end
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`define invalid_instruction state=`PROC_IF_STATE_ENTRY;EXCEPTION=1;
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always @(posedge clock) begin
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case(state)
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`PROC_HALT_STATE:
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HALT=1;
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`PROC_IF_STATE_ENTRY:begin
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EXCEPTION=0;
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external_address_bus <= ProgCount;
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read <= 0;
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write <= 1;
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state=`PROC_IF_WRITE_CIR;
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end
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`PROC_DE_STATE_ENTRY:begin
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external_address_bus <= ProgCount; /*Remenance from IF*/
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case(CIR[15:10])
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6'b100000 : begin
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/* ADD, ADC, SUB, SBB, CMP , AND, ... */
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case (CIR[5:3])
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3'b000 : begin
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/* Add Immediate to register/memory */
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in1_sel=2'b00;
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in2_sel=2'b01;
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out_sel=2'b01;
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PARAM2[2:0]=CIR[2:0];
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PARAM2[5:3]=CIR[2:0];
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state=`PROC_DE_LOAD_16_PARAM;
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end
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default:begin
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`invalid_instruction
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end
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endcase
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end
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6'b111111 : begin
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/* INC */
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if (CIR[9:9] == 1 ) begin
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case (CIR[5:3])
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3'b000 :begin
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/* Increment Register or Memmory */
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in1_sel=2'b00;
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in2_sel=2'b01;
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out_sel=2'b01;
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PARAM1=1;
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PARAM2[2:0]=CIR[2:0];
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PARAM2[5:3]=CIR[2:0];
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state=`PROC_EX_STATE_ENTRY;
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end
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default:begin
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`invalid_instruction
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end
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endcase
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end else begin
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`invalid_instruction
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end
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end
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default:begin
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`invalid_instruction
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end
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endcase
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end
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`PROC_DE_LOAD_16_PARAM:begin
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PARAM1 <= external_data_bus;
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ProgCount=ProgCount+1;
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state=`PROC_EX_STATE_ENTRY;
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end
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`PROC_EX_STATE_ENTRY:begin
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EXCEPTION=0;
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exec_unit_execute=0;
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state=`PROC_EX_STATE_EXIT;
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end
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endcase
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end
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endmodule
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