1966ab78b4
Peripherals/I2C: Added a CPU I2C driver and wrote a bootloader that uses that to boot from an I2C eeprom
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I'm happy to have reached 200 commits and with this, version v0.3.0 is functionally ready. I still need to do a fair bit of cleanup and bug fixing though before the actual release. With this commit I added a CPU I2C driver as well as a basic arbiter to have the hardware lcd controller and the software i2c communication pass through the same I2C driver and I2C bus. I also wrote a bootloader that reads code from an i2c eeprom to make sure the hardware works.
2024-02-09 23:30:58 +00:00
3e66336456
Build system: Small fixes and corrected rebuild when only the verilator testbench was changed
2023-12-09 02:39:14 +00:00
94bc6eba39
Build system: Added help text and target mrproper which also deletes downloaded source code
2023-12-08 22:10:11 +00:00
533f346f9b
Build system: Added the ability to simulate an FPGA SoC and fixed all the warning verilator gave of the code previously used only for synthesis.
2023-12-07 16:39:04 +00:00
b1108e375d
Build system: Fixed standalone ./system/Makefile build and general Makefile improvements
2023-12-06 18:13:24 +00:00
8edafd70cf
Build system: Improved the handling of seeds, moved most of the board specific build instructions to the board specific .mk file and fixed bios.asm dependencies
2023-12-05 21:46:56 +00:00
dd1080b42c
Build system: Added maximum CPU frequency to build system info and improved the way nextpnr seed is handled, fixing builds with older versions of make
2023-12-05 01:13:43 +00:00
0eecfdcf40
Tools/Gen_litedram: Major improvements and cleanup including work in ensuring it is reproducible
2023-12-04 21:36:48 +00:00
63ea29e399
Peripherals/Memory: Added support for the litedram DDR memory controller, created a new memory map and updated all relevant code and files including the addition of rudimentary wait state support for the cpu (BIU)
2023-12-03 19:24:39 +00:00
17638d5cbd
Build system: Slight improvements, randomised nextpnr rng seed and printed it to the terminal. In case timing fails running it a bunch of times can yield one value that passes.
2023-11-23 23:27:19 +00:00
aedefddb5d
Project: The cpu finally works perfectly now even at full speed as far as i can tell! I made the ram and register writes synchronous which fixed the weird issues I had, then I added -abc9 to yosys so that nextpnr can actually route the cpu at full speed and increased the display fifo since the cpu is so fast now!!
2023-11-15 18:43:56 +00:00
29bc2e6d96
Project: Cleaned up some code and run the project through aspell
2023-11-15 14:37:46 +00:00
2c8e8a9d9c
Added simple support for \n and \r on the HD44780 driver, increased the synthesised mem to fit brainfuck_compiled.asm and made it the default.
2023-11-12 21:39:27 +00:00
618c3102d8
Fixed some dependencies on the makefiles
2023-11-12 13:30:12 +00:00
e06c0eeaa0
Made the build system simplify the microcode so that yosys understands and synthesises it! Now gnome_sort.asm almost works!
2023-11-12 04:04:56 +00:00
4c130a8d63
Added back removed warnings to verilator since we have now fixed those issues
2023-11-12 00:07:33 +00:00
09b3d51015
Added statistics to place&route
2023-11-09 23:10:06 +00:00
a88c420ca5
Added an I2C driver, a PCF8574 driver and an HD44780 display driver. Unfortunately this shows that even fibonacci doesn't run correctly. Nonetheless, I made colored_led.asm output text to the display!
2023-11-09 22:10:55 +00:00
1a1634c673
Updated README, improved fpga-specific makefile options and updated the version number
2023-11-07 14:37:22 +00:00
01dcbfa7a1
The CPU works on real hardware for the first time! I added an adjustment for ram size, added control for a led and a test program for it. On the fpga board there is an actual led there that I used to verify functionality
2023-11-06 08:13:36 +00:00
08aac5c7b6
Removed some code that wasn't meant for synthesis and fixed important bug in Makefile
2023-11-02 22:19:15 +00:00
601397b7f0
Properly added fpga_top.v stuff in the build system and fixed some syntax errors
2023-11-02 22:00:07 +00:00
36bf8f9c7a
Added OrangeCrab board-specific code to connect the cpu to the outside world
2023-11-02 20:40:04 +00:00
5feee9de57
Added support to the build system for synthesising, place and routing, serialising and uploading the design to a Lattice ECP5 OrangeCrab FPGA
2023-11-02 00:29:14 +00:00
85512d5ace
Last minute fix of dependencies in Makefile before release
2023-11-01 19:09:59 +00:00
07d2a80b2e
Added code to record statistics and a tool to plot them
2023-05-14 16:06:33 +01:00
a8ab6b2dc7
Separated the execution unit from decode
2023-05-11 12:22:49 +01:00
da51dd6da7
First draft of a bus interface unit in an effort to make the CPU pipelined. Currently supports code prefetching
2023-05-07 13:34:15 +01:00
8070d4e58a
Improved build system's handling of verilator
2023-03-05 23:11:18 +00:00
99cbc49e95
Wrote a more complete testbench for verilator, switched from lx2 to fst and fixed cpu clock frequency calculation
2023-03-05 00:10:55 +00:00
5705b8e8a5
Added support for Verilator!
2023-03-04 08:37:43 +00:00
cac01f0333
Fixed Makefile bug
2023-02-22 01:51:14 +00:00
7fde422341
Added Microcode support, Stack, implemented the CALL instruction in microcode and grouped the wires on the decoder module
2023-02-22 01:28:23 +00:00
e2e9a92832
Cleaned the decoder a bit and laid down some of the groundwork for microcode
2023-02-19 16:22:23 +00:00
fd4a9b5442
Fixed register addressing bug, mem read endianness, cleaned up code and added a provisional project logo
2023-02-19 00:20:53 +00:00
82bd859874
Moved the decoding of opcodes into a separate module and optimised memory reads
2023-02-17 18:08:09 +00:00
ed3d7101d3
Further improved build system and changed brainfuck print message
2023-02-16 23:26:32 +00:00
ded47555a5
Improved build system and project directory structure
2023-02-16 01:52:02 +00:00
