9086/system/processor.v

/* processor.v - implementation of most functions of the 9086 processor

   This file is part of the 9086 project.

   Copyright (c) 2023 Efthymios Kritikos

   This program is free software: you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation, either version 3 of the License, or
   (at your option) any later version.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */

`include "exec_state_def.v"
`include "alu_header.v"
`include "config.v"
`include "ucode_header.v"
`include "error_header.v"

`define PROC_STATE_BITS		3
`define PROC_RESET		3'b000
`define PROC_DE_STATE_ENTRY	3'b001
`define PROC_HALT		3'b011

//HALT: active high
//IOMEM: 1=IO  0=MEM
//BHE: active low
//write: active low
//read: active low
//reset: active low

module processor (
	/*     MISC    */  input clock, input reset, output wire HALT,output [`ERROR_BITS-1:0] ERROR
	/* MEMORY / IO */ ,output [19:0] external_address_bus, inout [15:0] external_data_bus,output read, output write,output BHE,output IOMEM
`ifdef CALCULATE_IPC
	/*  STATISTICS */ ,output wire new_instruction
`endif
`ifdef OTUPUT_JSON_STATISTICS
	/*             */ ,output wire [`L1_CACHE_SIZE-1:0] L1_SIZE_STAT, output wire VALID_INSTRUCTION_STAT, output wire jump_req_debug
`endif
	);


`ifdef OTUPUT_JSON_STATISTICS
assign jump_req_debug=biu_jump_req;
`endif

/* If there is an error either from the decoder or execution unit set it to ERROR */
assign ERROR=(DE_ERROR!=`ERR_NO_ERROR)?DE_ERROR:(EXEC_ERROR!=`ERR_NO_ERROR)?EXEC_ERROR:`ERR_NO_ERROR;


/*############ Execution Unit ################################################### */

wire [1:0] in_alu_sel1, in_alu_sel2;
assign in_alu_sel1 = DE_OUTPUT[44:43];
assign in_alu_sel2 = DE_OUTPUT[46:45];

wire valid_exec_data, set_initial_values;

wire [`ERROR_BITS-1:0] EXEC_ERROR;

wire use_exec_reg_addr;

wire [3:0] EXEC_reg_read_port1_addr;
wire [15:0] ALU_O;
wire [7:0]EX2DE_FLAGS;

wire [15:0] PARAM1_INIT, PARAM2_INIT;
assign PARAM1_INIT = DE_OUTPUT[23:8];
assign PARAM2_INIT = DE_OUTPUT[39:24];

wire [2:0] IN_MOD,OUT_MOD;
assign IN_MOD=DE_OUTPUT[2:0];
assign OUT_MOD=DE_OUTPUT[49:47];

wire [`ALU_OP_BITS-1:0] ALU_OP;
assign ALU_OP = DE_OUTPUT[42:40];

wire [23:0] DE2EX_INSTRUCTION;

wire next_exec;
execute_unit execute_unit (
	/*    GENERAL    */ clock, reset, Wbit, Sbit, opcode_size, DE2EX_INSTRUCTION[23:0] , valid_exec_data
	/*               */ ,IN_MOD, OUT_MOD,memio_address_select, ProgCount, RM, EXEC_ERROR, write
	/*               */ ,set_initial_values,next_exec
	/*     PARAM     */ ,PARAM1_INIT,PARAM2_INIT
	/* STATE CONTROL */ ,next_state
        /*  ALU CONTROL  */ ,in_alu_sel1, in_alu_sel2, ALU_OP, ALU_O
	/* REGISTER DATA */ ,reg_read_port1_data, reg_read_port2_data, EXEC_reg_read_port1_addr, use_exec_reg_addr, reg_write_we
	/*     FLAGS     */ ,EX2DE_FLAGS
	/*      BIU      */ ,BIU_ADDRESS_INPUT, biu_write_request, biu_read_request, BIU_VALID_DATA, BIU_DATA, biu_data_direction, biu_jump_req
	);

/*############ Bus Interface Unit ############################################### */

wire [15:0] INSTRUCTION_LOCATION, BIU_ADDRESS_INPUT;
wire [15:0] BIU_DATA;
wire [31:0] INSTRUCTION;
wire biu_write_request, biu_read_request, BIU_VALID_DATA;
wire biu_jump_req, biu_data_direction,VALID_INSTRUCTION;
wire VALID_INSTRUCTION_ACK;

BIU BIU(
	/* Outside world */  clock,reset,external_address_bus
	/*               */ ,external_data_bus,read,write,BHE,IOMEM
	/*   Internal    */ ,INSTRUCTION,VALID_INSTRUCTION,INSTRUCTION_LOCATION,biu_jump_req
	/*               */ ,BIU_ADDRESS_INPUT,BIU_DATA,biu_write_request,biu_read_request,Wbit,BIU_VALID_DATA,MEM_OR_IO
	/*               */ ,VALID_INSTRUCTION_ACK
`ifdef OTUPUT_JSON_STATISTICS
	/*  Statistics   */ ,L1_SIZE_STAT, VALID_INSTRUCTION_STAT
`endif
	);

assign BIU_DATA= biu_data_direction ? 16'hz : (memio_address_select ? reg_read_port1_data : ALU_O);

/*############ Decoder ########################################################## */


wire [`EXEC_STATE_BITS+`ERROR_BITS+65:0] DE_OUTPUT;

decoder decoder(
	/* GENERAL       */ clock, reset,
	/* INPUT FROM IF */ INSTRUCTION,VALID_INSTRUCTION,INSTRUCTION_LOCATION
	/* INPUT FROM EX */ ,EX2DE_FLAGS[7:0],next_exec
	/* OUTPUT TO EX  */ ,DE_OUTPUT,DE2EX_INSTRUCTION
	/*               */ ,ProgCount,set_initial_values,valid_exec_data
	/* OUTPUT TO IF  */ ,VALID_INSTRUCTION_ACK
`ifdef CALCULATE_IPC
	/* STATISTICS    */ , new_instruction
`endif
	);

wire [2:0] RM;
assign RM = DE_OUTPUT[5:3];

wire  memio_address_select;
assign memio_address_select=DE_OUTPUT[6:6];

wire [3:0] DE_reg_read_port1_addr,DE_reg_read_port2_addr;
assign DE_reg_read_port1_addr=DE_OUTPUT[53:50];
assign DE_reg_read_port2_addr=DE_OUTPUT[57:54];

wire [3:0] reg_write_addr;
assign reg_write_addr=DE_OUTPUT[61:58];

wire MEM_OR_IO;
assign MEM_OR_IO = DE_OUTPUT[7:7];

wire Wbit, Sbit, opcode_size;
assign opcode_size=DE_OUTPUT[62:62];
assign Sbit=DE_OUTPUT[63:63];
assign Wbit=DE_OUTPUT[64:64];

wire [`ERROR_BITS-1:0] DE_ERROR;
assign HALT = DE_OUTPUT[65:65];
assign DE_ERROR = DE_OUTPUT[`ERROR_BITS+65:66];

wire [`EXEC_STATE_BITS-1:0] next_state;
assign next_state=DE_OUTPUT[`EXEC_STATE_BITS+`ERROR_BITS+65:`ERROR_BITS+66];

/*############ Registers ######################################################## */

wire [15:0] ProgCount;

wire [3:0] reg_read_port1_addr;
assign reg_read_port1_addr = use_exec_reg_addr ? EXEC_reg_read_port1_addr : DE_reg_read_port1_addr;

wire [15:0] reg_read_port1_data, reg_read_port2_data;

wire reg_write_we;

register_file register_file(
	/*   WRITE  */ .write_port1_addr(reg_write_addr),
	/*          */ .write_port1_data(ALU_O),
	/*          */ .write_port1_we(reg_write_we),
	/*  READ 1  */ .read_port1_addr(reg_read_port1_addr),
	/*          */ .read_port1_data(reg_read_port1_data),
	/*  READ 2  */ .read_port2_addr(DE_reg_read_port2_addr),
	/*          */ .read_port2_data(reg_read_port2_data)
	);

/*############################################################################### */


endmodule