9086/cpu/processor.v

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`include "proc_state_def.v"
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module exec_units ( input [15:0]PARAM1, input [15:0]PARAM2, input [1:0]in1_sel, input [1:0]in2_sel, input [1:0]out_sel , input EXEC);
/*Architectural Register file*/
wire [2:0] reg_addr;
wire [15:0] reg_data;
wire reg_read;
wire reg_write;
wire [2:0] reg_read_addr;
wire [15:0] reg_read_data;
wire reg_read_read;
register_file register_file(reg_addr,reg_data,reg_read,reg_write,reg_read_addr,reg_read_data,reg_read_read);
/*Exec Unts*/
wire [15:0] ADDER16_1A;
wire [15:0] ADDER16_1B;
wire [15:0] ADDER16_1O;
wire ADDER16_1C;
ADDER16 ADDER16_1(ADDER16_1A,ADDER16_1B,EXEC,ADDER16_1O,ADDER16_1C);
/*logic*/
assign reg_addr=PARAM2[5:3];
assign reg_read=EXEC;
assign reg_write=EXEC;
assign reg_read_read=0;
assign reg_read_addr=PARAM2[2:0];
assign ADDER16_1A= (in1_sel==2'b00) ? PARAM1 : 16'b1010101010101010;
assign ADDER16_1B= (in2_sel==2'b01) ? reg_read_data : 16'b1010101010101010;
//assign reg_data = (out_sel==2'b01) ? ADDER16_1O : 'hz;
//assign reg_data = (out_sel==2'b01) ? ADDER16_1O : ADDER16_1O;
assign reg_data = ADDER16_1O;
endmodule
module processor ( input clock, input reset , output reg [19:0] external_address_bus, inout [15:0] external_data_bus,output reg read, output reg write, output reg HALT);
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/* State */
reg [3:0] state;
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reg instruction_finished;
/* Registers */
reg [19:0] ProgCount;
reg [15:0] CIR;
reg [15:0] PARAM1;
reg [15:0] PARAM2;
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/* Execution units*/
reg [1:0] in1_sel;
reg [1:0] in2_sel;
reg [1:0] out_sel;
reg exec_unit_execute;
exec_units exec_units(PARAM1,PARAM2,in1_sel,in2_sel,out_sel,exec_unit_execute);
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/* RESET LOGIC */
always @(negedge reset) begin
if (reset==0) begin
@(posedge clock);
ProgCount=0;//TODO: Reset Vector
EXCEPTION=0;
HALT=0;
exec_unit_execute=1;
@(negedge clock);
@(posedge clock);
state=`PROC_IF_STATE_ENTRY;
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end
end
reg EXCEPTION;
/* Processor stages */
always @(negedge clock) begin
case(state)
`PROC_IF_WRITE_CIR:begin
CIR <= external_data_bus;
ProgCount=ProgCount+1;
state=`PROC_DE_STATE_ENTRY;
end
`PROC_EX_STATE_EXIT:begin
exec_unit_execute=1;
state=`PROC_IF_STATE_ENTRY;
end
endcase
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end
`define invalid_instruction state=`PROC_IF_STATE_ENTRY;EXCEPTION=1;
always @(posedge clock) begin
case(state)
`PROC_HALT_STATE:
HALT=1;
`PROC_IF_STATE_ENTRY:begin
EXCEPTION=0;
external_address_bus <= ProgCount;
read <= 0;
write <= 1;
state=`PROC_IF_WRITE_CIR;
end
`PROC_DE_STATE_ENTRY:begin
external_address_bus <= ProgCount; /*Remenance from IF*/
case(CIR[15:10])
6'b100000 : begin
/* ADD, ADC, SUB, SBB, CMP , AND, ... */
case (CIR[5:3])
3'b000 : begin
/* Add Immediate to register/memory */
in1_sel=2'b00;
in2_sel=2'b01;
out_sel=2'b01;
PARAM2[2:0]=CIR[2:0];
PARAM2[5:3]=CIR[2:0];
state=`PROC_DE_LOAD_16_PARAM;
end
default:begin
`invalid_instruction
end
endcase
end
6'b111111 : begin
/* INC */
if (CIR[9:9] == 1 ) begin
case (CIR[5:3])
3'b000 :begin
/* Increment Register or Memmory */
in1_sel=2'b00;
in2_sel=2'b01;
out_sel=2'b01;
PARAM1=1;
PARAM2[2:0]=CIR[2:0];
PARAM2[5:3]=CIR[2:0];
state=`PROC_EX_STATE_ENTRY;
end
default:begin
`invalid_instruction
end
endcase
end else begin
`invalid_instruction
end
end
default:begin
`invalid_instruction
end
endcase
end
`PROC_DE_LOAD_16_PARAM:begin
PARAM1 <= external_data_bus;
ProgCount=ProgCount+1;
state=`PROC_EX_STATE_ENTRY;
end
`PROC_EX_STATE_ENTRY:begin
EXCEPTION=0;
exec_unit_execute=0;
state=`PROC_EX_STATE_EXIT;
end
endcase
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end
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endmodule