2023-02-09 14:46:21 +00:00
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`include "proc_state_def.v"
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2023-02-11 14:43:53 +00:00
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`include "alu_header.v"
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2023-02-13 15:24:21 +00:00
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`include "config.v"
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2023-02-08 09:18:00 +00:00
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2023-02-10 01:45:27 +00:00
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module mux4 (in1,in2,in3,in4, sel,out);
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input [0:1] sel;
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parameter WIDTH=16;
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input [WIDTH-1:0] in1,in2,in3,in4;
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output [WIDTH-1:0] out;
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assign out = (sel == 'b00) ? in1 :
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(sel == 'b01) ? in2 :
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(sel == 'b10) ? in3 :
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in4;
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2023-02-09 20:16:50 +00:00
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endmodule
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2023-02-11 01:05:19 +00:00
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module processor ( input clock, input reset, output reg [19:0] external_address_bus, inout [15:0] external_data_bus,output reg read, output reg write, output reg HALT,output reg ERROR);
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2023-02-09 20:16:50 +00:00
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2023-02-10 01:45:27 +00:00
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/*** Global Definitions ***/
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// State
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2023-02-09 14:46:21 +00:00
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reg [3:0] state;
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2023-02-08 12:07:42 +00:00
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2023-02-10 01:45:27 +00:00
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// Registers
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2023-02-08 12:07:42 +00:00
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reg [19:0] ProgCount;
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2023-02-09 14:46:21 +00:00
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reg [15:0] CIR;
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reg [15:0] PARAM1;
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reg [15:0] PARAM2;
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2023-02-10 12:02:20 +00:00
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reg unaligned_access;
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2023-02-11 20:27:28 +00:00
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reg [1:0]IN_MOD;
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reg [2:0]IN_RM;
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reg Wbit;
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2023-02-12 01:05:39 +00:00
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reg [15:0]FLAGS;
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/* . . . . O D I T S Z . A . P . C */
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// C - Carry flag : carry out or borrow into the high order bit (8bit/16bit)
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//
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// P - Parity flag : is set if result has even parity
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//
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// A - Auxiliary flag : carry out from the low nibble to the high nibble or
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// an equiv borrow. Used by decimal arithmetic instructions
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//
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// Z - Zero flag : Set when result of Operation is zero
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//
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// S - Sign flag : set if the high order bit of the result is 1. aka the sign
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// of the result
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//
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// T - Trap flag : Set the cpu into single step mode where it generates an
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// interrupt after each instruction
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//
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// I - Interrupt flag : 0: interrupts are masked
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//
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// D - Direction flag : 1: string instructions decrement 0: they increment
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//
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// O - Overflow flag : set on arythmetic overflow
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2023-02-08 12:07:42 +00:00
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2023-02-10 01:45:27 +00:00
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// Execution units
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2023-02-09 20:16:50 +00:00
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reg [1:0] in1_sel;
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reg [1:0] in2_sel;
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2023-02-13 10:36:37 +00:00
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/* out_sel : { EXTRA_FUNCTIONS_BIT[0:0], MOD_OR_EXTRA_FUNCTION[1:0] } */
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reg [2:0] out_sel;
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2023-02-09 20:16:50 +00:00
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2023-02-10 01:45:27 +00:00
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/*** RESET LOGIC ***/
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2023-02-08 12:07:42 +00:00
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always @(negedge reset) begin
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if (reset==0) begin
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@(posedge clock);
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2023-02-10 18:20:28 +00:00
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state=`PROC_HALT_STATE;
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2023-02-08 12:07:42 +00:00
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ProgCount=0;//TODO: Reset Vector
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2023-02-09 14:46:21 +00:00
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HALT=0;
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2023-02-11 13:41:12 +00:00
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reg_write_we=1;
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reg_read_oe=1;
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2023-02-10 12:02:20 +00:00
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unaligned_access=0;
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2023-02-11 14:43:53 +00:00
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ALU_1OE=1;
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2023-02-10 18:20:28 +00:00
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@(posedge reset)
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2023-02-09 14:46:21 +00:00
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@(negedge clock);
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state=`PROC_IF_STATE_ENTRY;
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2023-02-11 20:27:28 +00:00
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IN_MOD=2'b11;
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2023-02-13 15:24:21 +00:00
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ERROR=0;
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2023-02-08 12:07:42 +00:00
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end
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end
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2023-02-10 01:45:27 +00:00
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/*** ALU and EXEC stage logic ***/
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//Architectural Register file
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2023-02-11 13:41:12 +00:00
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reg [3:0] reg_write_addr;
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reg [15:0] reg_write_data;
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reg reg_write_we;
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reg [3:0] reg_read_addr;
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2023-02-10 01:45:27 +00:00
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reg [15:0] reg_read_data;
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2023-02-11 13:41:12 +00:00
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reg reg_read_oe;
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register_file register_file(reg_write_addr,reg_write_data,reg_write_we,reg_read_addr,reg_read_data,reg_read_oe);
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2023-02-10 01:45:27 +00:00
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//ALU
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mux4 #(.WIDTH(16)) MUX16_1A(
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PARAM1,
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2023-02-11 14:43:53 +00:00
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reg_read_data,
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2023-02-13 10:36:37 +00:00
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{ProgCount[14:0],unaligned_access}, /*THATS NOT ALL OF ADDR Bus, is that irrelevant with segmentation??*/
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2023-02-10 01:45:27 +00:00
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16'b0,
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in1_sel,
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2023-02-11 14:43:53 +00:00
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ALU_1A);
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2023-02-10 01:45:27 +00:00
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mux4 #(.WIDTH(16)) MUX16_1B(
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2023-02-10 15:30:59 +00:00
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PARAM2,
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2023-02-10 01:45:27 +00:00
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reg_read_data,
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2023-02-13 10:36:37 +00:00
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{ProgCount[14:0],unaligned_access}, /*THATS NOT ALL OF ADDR Bus, is that irrelevant with segmentation??*/
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2023-02-10 01:45:27 +00:00
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16'b0,
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in2_sel,
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2023-02-11 14:43:53 +00:00
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ALU_1B);
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2023-02-10 01:45:27 +00:00
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2023-02-11 14:43:53 +00:00
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wire [15:0] ALU_1A;
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wire [15:0] ALU_1B;
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wire [15:0] ALU_1O;
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reg [`ALU_OP_BITS-1:0]ALU_1OP;
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reg ALU_1OE;
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2023-02-12 01:05:39 +00:00
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wire [7:0] ALU_FLAGS;
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ALU ALU(ALU_1A,ALU_1B,ALU_1OE,ALU_1O,ALU_1OP,ALU_FLAGS,Wbit);
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2023-02-10 01:45:27 +00:00
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/*** Processor stages ***/
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2023-02-10 14:39:34 +00:00
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2023-02-11 20:27:28 +00:00
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`define invalid_instruction state=`PROC_IF_STATE_ENTRY;ERROR=1;IN_MOD=2'b11;
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`define start_aligning_instruction if(unaligned_access==0)begin ProgCount=ProgCount+1; external_address_bus <= ProgCount; end /*we normally don't advance PC in case of singly byte unaligning instructions leasving us with two instructions in one read so do that here*/
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`define start_unaligning_instruction unaligned_access=~unaligned_access;
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2023-02-10 14:39:34 +00:00
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2023-02-09 14:46:21 +00:00
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always @(negedge clock) begin
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case(state)
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`PROC_IF_WRITE_CIR:begin
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2023-02-10 12:02:20 +00:00
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if(unaligned_access)begin
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CIR[15:8] <= external_data_bus[7:0];
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ProgCount=ProgCount+1;
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state=`PROC_IF_STATE_EXTRA_FETCH_SET;
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end else begin
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CIR <= external_data_bus;
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state=`PROC_DE_STATE_ENTRY;
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end
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end
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`PROC_IF_STATE_EXTRA_FETCH:begin
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2023-02-11 14:43:53 +00:00
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CIR[7:0] <= external_data_bus[15:8];
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state=`PROC_DE_STATE_ENTRY;
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2023-02-09 14:46:21 +00:00
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end
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2023-02-09 20:16:50 +00:00
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`PROC_EX_STATE_EXIT:begin
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2023-02-13 10:36:37 +00:00
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case(out_sel)
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3'b011:begin
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reg_write_we=0;
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state=`PROC_IF_STATE_ENTRY;
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end
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3'b101:begin
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ProgCount=ALU_1O[15:1];
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unaligned_access=ALU_1O[0:0];
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state=`PROC_IF_STATE_ENTRY;
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end
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3'b100:begin
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state=`PROC_IF_STATE_ENTRY;
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end
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default:begin
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`invalid_instruction
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end
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endcase
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2023-02-09 20:16:50 +00:00
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end
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2023-02-10 12:02:20 +00:00
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`PROC_DE_LOAD_16_EXTRA_FETCH_SET:begin
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external_address_bus = ProgCount;
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state=`PROC_DE_LOAD_16_EXTRA_FETCH;
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end
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2023-02-11 20:27:28 +00:00
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`PROC_MEMIO_SETADDR:begin
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external_address_bus = {1'b0,reg_read_data[15:1]};
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state=reg_read_data[0:0]?`PROC_MEMIO_GET_UNALIGNED_DATA:`PROC_MEMIO_GET_ALIGNED_DATA;
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end
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2023-02-09 14:46:21 +00:00
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endcase
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2023-02-08 12:07:42 +00:00
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end
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2023-02-09 14:46:21 +00:00
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always @(posedge clock) begin
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case(state)
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2023-02-10 18:20:28 +00:00
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`PROC_HALT_STATE:begin
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end
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2023-02-09 14:46:21 +00:00
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`PROC_IF_STATE_ENTRY:begin
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2023-02-13 15:24:21 +00:00
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`ifdef DEBUG_PC_ADDRESS
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/* Weird (possible bug) where even though the
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* testbench stop the clock after ERROR gets
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* raised the logic for the rising edge still
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* gets triggered printing this debug message. */
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if(ERROR!=1)
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$display("Fetched instruction at %04x",{ProgCount[18:0],unaligned_access});
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`endif
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2023-02-09 14:46:21 +00:00
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external_address_bus <= ProgCount;
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read <= 0;
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write <= 1;
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2023-02-11 13:41:12 +00:00
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reg_read_oe=1;
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reg_write_we=1;
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2023-02-11 14:43:53 +00:00
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ALU_1OE=1;
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2023-02-09 14:46:21 +00:00
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state=`PROC_IF_WRITE_CIR;
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end
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2023-02-10 12:02:20 +00:00
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`PROC_IF_STATE_EXTRA_FETCH_SET:begin
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external_address_bus <= ProgCount;
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state=`PROC_IF_STATE_EXTRA_FETCH;
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end
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2023-02-11 20:27:28 +00:00
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/* 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 */
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2023-02-11 13:41:12 +00:00
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/* AFTER THE IF STAGE WE HAVE THE FRIST BYTE OF THE
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* INSTRUCTION ADN THE ONE FOLLOWING, ALLIGNED CORRECTLY TO
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* CIR */
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2023-02-09 14:46:21 +00:00
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`PROC_DE_STATE_ENTRY:begin
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case(CIR[15:10])
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2023-02-10 12:02:20 +00:00
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6'b000001 : begin
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/* ADD, ... */
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if ( CIR[9:9] == 0 )begin
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2023-02-11 20:27:28 +00:00
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/* Add Immediate word/byte to accumulator */
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/* 0 0 0 0 0 1 0 W | DATA | DATA if W |*/
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Wbit=CIR[8:8];
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if(Wbit)
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`start_unaligning_instruction
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else
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`start_aligning_instruction
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IN_MOD=2'b11;
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2023-02-10 12:02:20 +00:00
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in1_sel=2'b00;
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in2_sel=2'b01;
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2023-02-13 10:36:37 +00:00
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out_sel=3'b011;
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2023-02-11 13:41:12 +00:00
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reg_read_addr={CIR[8:8],3'b000};
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reg_write_addr={CIR[8:8],3'b000};
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reg_read_oe=0;
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2023-02-11 14:43:53 +00:00
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ALU_1OE=0;
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ALU_1OP=`ALU_OP_ADD;
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2023-02-11 13:41:12 +00:00
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if(CIR[8:8]==1)
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state=`PROC_DE_LOAD_16_PARAM;
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else begin
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2023-02-12 01:05:39 +00:00
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PARAM1[7:0]=CIR[7:0];
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state=`PROC_EX_STATE_ENTRY;
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2023-02-11 13:41:12 +00:00
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end
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2023-02-10 12:02:20 +00:00
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end else begin
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`invalid_instruction
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end
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end
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2023-02-09 14:46:21 +00:00
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6'b100000 : begin
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2023-02-09 20:16:50 +00:00
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/* ADD, ADC, SUB, SBB, CMP , AND, ... */
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2023-02-09 14:46:21 +00:00
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case (CIR[5:3])
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2023-02-09 20:16:50 +00:00
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3'b000 : begin
|
2023-02-11 13:41:12 +00:00
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/* Add Immediate word/byte to register/memory */
|
2023-02-11 20:27:28 +00:00
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/* 1 0 0 0 0 0 S W | MOD 0 0 0 R/M | < DISP LO > | < DISP HI > | DATA | DATA if W | */
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`start_aligning_instruction
|
2023-02-12 01:28:37 +00:00
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Wbit=CIR[8:8];
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2023-02-11 20:27:28 +00:00
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IN_MOD=2'b11;
|
2023-02-09 20:16:50 +00:00
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in1_sel=2'b00;
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in2_sel=2'b01;
|
2023-02-13 10:36:37 +00:00
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out_sel={1'b0,CIR[7:6]};
|
2023-02-11 13:41:12 +00:00
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reg_read_addr={CIR[8:8],CIR[2:0]};
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reg_write_addr={CIR[8:8],CIR[2:0]};
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reg_read_oe=0;
|
2023-02-11 14:43:53 +00:00
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ALU_1OE=0;
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ALU_1OP=`ALU_OP_ADD;
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2023-02-09 14:46:21 +00:00
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state=`PROC_DE_LOAD_16_PARAM;
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2023-02-11 13:41:12 +00:00
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if(CIR[8:8]==1)
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state=`PROC_DE_LOAD_16_PARAM;
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else begin
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`invalid_instruction /*do 8bit loads*/
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end
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2023-02-09 14:46:21 +00:00
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end
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default:begin
|
2023-02-09 20:16:50 +00:00
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`invalid_instruction
|
2023-02-09 14:46:21 +00:00
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end
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endcase
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end
|
2023-02-10 15:30:59 +00:00
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6'b101100,
|
2023-02-11 13:41:12 +00:00
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6'b101101:begin
|
2023-02-11 20:27:28 +00:00
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/* MOV - Move Immediate byte to register */
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/* 1 0 1 1 W REG | DATA | DATA if W |*/
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Wbit=CIR[11:11];
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if(Wbit)
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`start_unaligning_instruction
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else
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`start_aligning_instruction
|
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IN_MOD=2'b11;
|
2023-02-11 13:41:12 +00:00
|
|
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in1_sel=2'b00;
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in2_sel=2'b00;
|
2023-02-13 10:36:37 +00:00
|
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|
out_sel=3'b011;
|
2023-02-11 13:41:12 +00:00
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|
reg_write_addr={1'b0,CIR[10:8]};
|
|
|
|
PARAM1[7:0]=CIR[7:0];
|
|
|
|
PARAM2=0;
|
2023-02-11 14:43:53 +00:00
|
|
|
ALU_1OE=0;
|
|
|
|
ALU_1OP=`ALU_OP_ADD;
|
2023-02-11 13:41:12 +00:00
|
|
|
state=`PROC_EX_STATE_ENTRY;
|
|
|
|
end
|
2023-02-10 15:30:59 +00:00
|
|
|
6'b101110,
|
2023-02-11 13:41:12 +00:00
|
|
|
6'b101111 : begin
|
2023-02-11 20:27:28 +00:00
|
|
|
/*MOV - Move Immediate word to register*/
|
|
|
|
Wbit=CIR[11:11];
|
|
|
|
if(Wbit)
|
|
|
|
`start_unaligning_instruction
|
|
|
|
else
|
|
|
|
`start_aligning_instruction
|
|
|
|
IN_MOD=2'b11;
|
2023-02-10 15:30:59 +00:00
|
|
|
in1_sel=2'b00;
|
|
|
|
in2_sel=2'b00;
|
2023-02-13 10:36:37 +00:00
|
|
|
out_sel=3'b011;
|
2023-02-11 13:41:12 +00:00
|
|
|
reg_write_addr={1'b1,CIR[10:8]};
|
2023-02-11 14:43:53 +00:00
|
|
|
ALU_1OE=0;
|
|
|
|
ALU_1OP=`ALU_OP_ADD;
|
2023-02-10 15:30:59 +00:00
|
|
|
PARAM2=0;
|
|
|
|
state=`PROC_DE_LOAD_16_PARAM;
|
|
|
|
end
|
2023-02-11 20:27:28 +00:00
|
|
|
|
|
|
|
6'b100010 : begin
|
|
|
|
/* MOV - Reg/Mem to/from register */
|
|
|
|
/* 1 0 0 0 1 0 D W | MOD REG REG | < DISP LO > | < DISP HI > |*/
|
|
|
|
`start_aligning_instruction
|
|
|
|
IN_MOD=CIR[7:6];
|
|
|
|
IN_RM=CIR[2:0];
|
|
|
|
Wbit=CIR[8:8];
|
|
|
|
if(CIR[9:9] == 1)begin
|
|
|
|
/* to reg */
|
|
|
|
IN_MOD=CIR[7:6];
|
|
|
|
if(IN_MOD==2'b11)begin
|
|
|
|
in1_sel=2'b01;
|
|
|
|
reg_read_addr=CIR[2:0];
|
|
|
|
end else begin
|
|
|
|
in1_sel=2'b00;
|
|
|
|
end
|
|
|
|
in2_sel=2'b00;
|
2023-02-13 10:36:37 +00:00
|
|
|
out_sel=3'b011;
|
2023-02-11 20:27:28 +00:00
|
|
|
reg_write_addr={CIR[8:8],CIR[5:3]};
|
|
|
|
end else begin
|
|
|
|
`invalid_instruction
|
|
|
|
end
|
|
|
|
|
|
|
|
ALU_1OE=0;
|
|
|
|
ALU_1OP=`ALU_OP_ADD;
|
|
|
|
PARAM2=0;
|
|
|
|
state=`PROC_DE_LOAD_16_PARAM;
|
|
|
|
if ( IN_MOD == 2'b11 )
|
|
|
|
state=`PROC_EX_STATE_ENTRY;
|
|
|
|
else
|
|
|
|
state=`RPOC_MEMIO_READ;
|
|
|
|
end
|
2023-02-11 14:43:53 +00:00
|
|
|
6'b010000,//INC
|
|
|
|
6'b010001,//INC
|
|
|
|
6'b010010,//DEC
|
|
|
|
6'b010011:begin//DEC
|
2023-02-11 20:27:28 +00:00
|
|
|
/* DEC - Decrement Register */
|
|
|
|
/* | 0 1 0 0 1 REG | */
|
|
|
|
/* INC - Increment Register */
|
|
|
|
/* | 0 1 0 0 0 REG | */
|
|
|
|
`start_unaligning_instruction
|
2023-02-12 01:28:37 +00:00
|
|
|
Wbit=1;
|
2023-02-11 14:43:53 +00:00
|
|
|
in1_sel=2'b01;
|
|
|
|
in2_sel=2'b00;
|
2023-02-13 10:36:37 +00:00
|
|
|
out_sel=3'b011;
|
2023-02-11 20:27:28 +00:00
|
|
|
IN_MOD=2'b11;
|
2023-02-11 14:43:53 +00:00
|
|
|
PARAM2=1;
|
|
|
|
reg_read_addr={1'b1,CIR[10:8]};
|
|
|
|
reg_write_addr={1'b1,CIR[10:8]};
|
|
|
|
reg_read_oe=0;
|
|
|
|
ALU_1OE=0;
|
|
|
|
if(CIR[11:11]==0)
|
|
|
|
ALU_1OP=`ALU_OP_ADD;
|
|
|
|
else
|
|
|
|
ALU_1OP=`ALU_OP_SUB;
|
|
|
|
state=`PROC_EX_STATE_ENTRY;
|
|
|
|
end
|
2023-02-09 14:46:21 +00:00
|
|
|
6'b111111 : begin
|
2023-02-09 20:16:50 +00:00
|
|
|
/* INC */
|
2023-02-09 14:46:21 +00:00
|
|
|
if (CIR[9:9] == 1 ) begin
|
|
|
|
case (CIR[5:3])
|
|
|
|
3'b000 :begin
|
2023-02-11 20:27:28 +00:00
|
|
|
/* INC - Register/Memory */
|
|
|
|
/* 1 1 1 1 1 1 1 W | MOD 0 0 0 R/M | < DISP LO> | < DISP HI> */
|
|
|
|
`start_aligning_instruction
|
2023-02-12 01:28:37 +00:00
|
|
|
Wbit=CIR[8:8];
|
2023-02-11 20:27:28 +00:00
|
|
|
IN_MOD=CIR[7:6];
|
|
|
|
in1_sel=2'b00;/* number 1 */
|
|
|
|
in2_sel=(CIR[7:6]==2'b11)? 2'b01 : 2'b00;
|
2023-02-13 10:36:37 +00:00
|
|
|
out_sel={1'b0,CIR[7:6]};
|
2023-02-09 20:16:50 +00:00
|
|
|
PARAM1=1;
|
2023-02-11 13:41:12 +00:00
|
|
|
reg_read_addr={1'b0,CIR[2:0]};
|
|
|
|
reg_write_addr={1'b0,CIR[2:0]};
|
|
|
|
reg_read_oe=0;
|
2023-02-11 14:43:53 +00:00
|
|
|
ALU_1OE=0;
|
|
|
|
ALU_1OP=`ALU_OP_ADD;
|
2023-02-11 20:27:28 +00:00
|
|
|
if ( CIR[7:6] == 2'b11 )
|
|
|
|
state=`PROC_EX_STATE_ENTRY;
|
|
|
|
else
|
|
|
|
state=`RPOC_MEMIO_READ;
|
2023-02-09 14:46:21 +00:00
|
|
|
end
|
|
|
|
default:begin
|
2023-02-09 20:16:50 +00:00
|
|
|
`invalid_instruction
|
2023-02-09 14:46:21 +00:00
|
|
|
end
|
|
|
|
endcase
|
|
|
|
end else begin
|
2023-02-09 20:16:50 +00:00
|
|
|
`invalid_instruction
|
2023-02-09 14:46:21 +00:00
|
|
|
end
|
|
|
|
end
|
2023-02-10 18:20:28 +00:00
|
|
|
6'b111101 : begin
|
|
|
|
/*HLT, CMC, TEST, NOT, NEG, MUL, IMUL, .... */
|
|
|
|
case (CIR[9:8])
|
|
|
|
2'b00:begin
|
2023-02-11 20:27:28 +00:00
|
|
|
/* HLT - Halt */
|
|
|
|
/* 1 1 1 1 0 1 0 0 | */
|
|
|
|
`start_unaligning_instruction
|
|
|
|
IN_MOD=2'b11;
|
2023-02-10 18:20:28 +00:00
|
|
|
HALT=1;
|
|
|
|
state=`PROC_HALT_STATE;
|
|
|
|
end
|
|
|
|
default:begin
|
|
|
|
`invalid_instruction;
|
|
|
|
end
|
|
|
|
endcase
|
|
|
|
|
|
|
|
end
|
2023-02-12 01:05:39 +00:00
|
|
|
6'b001111 : begin
|
|
|
|
if ( CIR[9:9] == 0 ) begin
|
|
|
|
/* CMP - Compare Immediate with accumulator */
|
|
|
|
/* 0 0 1 1 1 1 0 W | DATA | DATA if W |*/
|
|
|
|
/* */
|
|
|
|
/* NOTE: 8086 doc doesn't show the third byte but the */
|
|
|
|
/* W flag and my assembler seem to disagree */
|
|
|
|
Wbit=CIR[8:8];
|
|
|
|
if(Wbit)
|
|
|
|
`start_unaligning_instruction
|
|
|
|
else
|
|
|
|
`start_aligning_instruction
|
|
|
|
IN_MOD=2'b11;
|
|
|
|
in1_sel=2'b00;
|
|
|
|
in2_sel=2'b01;
|
|
|
|
reg_read_addr={CIR[8:8],3'b000};
|
|
|
|
reg_read_oe=0;
|
2023-02-13 10:36:37 +00:00
|
|
|
out_sel=3'b100;
|
2023-02-12 01:05:39 +00:00
|
|
|
ALU_1OE=0;
|
|
|
|
ALU_1OP=`ALU_OP_SUB;
|
|
|
|
if(CIR[8:8]==1)
|
|
|
|
state=`PROC_DE_LOAD_16_PARAM;
|
|
|
|
else begin
|
|
|
|
PARAM1[7:0]=CIR[7:0];
|
|
|
|
state=`PROC_EX_STATE_ENTRY;
|
|
|
|
end
|
|
|
|
end else begin
|
|
|
|
`invalid_instruction
|
|
|
|
end
|
|
|
|
end
|
2023-02-13 10:36:37 +00:00
|
|
|
6'b011100,
|
|
|
|
6'b011101,
|
|
|
|
6'b011110,
|
|
|
|
6'b011111:begin
|
|
|
|
/* Conditional relative jumps */
|
|
|
|
/* Jump on Zero */
|
|
|
|
/* 0 1 1 1 0 1 0 0 | IP-INC8 |*/
|
|
|
|
/* Jump on Sign */
|
|
|
|
/* 0 1 1 1 1 0 0 0 | IP-INC8 |*/
|
|
|
|
/* Jump on not Sign */
|
|
|
|
/* 0 1 1 1 1 0 0 1 | IP-INC8 |*/
|
|
|
|
/* .... */
|
|
|
|
`start_aligning_instruction
|
|
|
|
Wbit=1;
|
|
|
|
in1_sel=2'b10;
|
|
|
|
in2_sel=2'b00;
|
|
|
|
PARAM2={8'b00000000,CIR[7:0]};
|
|
|
|
ALU_1OE=0;
|
|
|
|
ALU_1OP=`ALU_OP_ADD;
|
|
|
|
out_sel=3'b101;
|
|
|
|
if(CIR[7:7]==1) begin
|
|
|
|
`invalid_instruction; // We don't do singed add 8bit to unsigned 16bit
|
|
|
|
end else begin
|
|
|
|
case(CIR[11:9])
|
|
|
|
4'b000: begin
|
|
|
|
/* Jump on (not) Overflow */
|
|
|
|
if(FLAGS[11:11]==CIR[8:8])
|
|
|
|
state=`PROC_IF_STATE_ENTRY;
|
|
|
|
else begin
|
|
|
|
state=`PROC_EX_STATE_ENTRY;
|
|
|
|
end
|
|
|
|
end
|
|
|
|
4'b010: begin
|
|
|
|
/* Jump on (not) Zero */
|
|
|
|
if(FLAGS[6:6]==CIR[8:8])
|
|
|
|
state=`PROC_IF_STATE_ENTRY;
|
|
|
|
else
|
|
|
|
state=`PROC_EX_STATE_ENTRY;
|
|
|
|
end
|
|
|
|
4'b100: begin
|
|
|
|
/* Jump on (not) Sign */
|
|
|
|
if(FLAGS[7:7]==CIR[8:8])
|
|
|
|
state=`PROC_IF_STATE_ENTRY;
|
|
|
|
else
|
|
|
|
state=`PROC_EX_STATE_ENTRY;
|
|
|
|
end
|
|
|
|
4'b101: begin
|
|
|
|
/* Jump on (not) Parity */
|
|
|
|
if(FLAGS[2:2]==CIR[8:8])
|
|
|
|
state=`PROC_IF_STATE_ENTRY;
|
|
|
|
else
|
|
|
|
state=`PROC_EX_STATE_ENTRY;
|
|
|
|
end
|
|
|
|
default:begin
|
|
|
|
`invalid_instruction; /*We don't support that condition*/
|
|
|
|
end
|
|
|
|
endcase
|
|
|
|
end
|
|
|
|
end
|
2023-02-09 14:46:21 +00:00
|
|
|
default:begin
|
2023-02-09 20:16:50 +00:00
|
|
|
`invalid_instruction
|
2023-02-09 14:46:21 +00:00
|
|
|
end
|
|
|
|
endcase
|
|
|
|
end
|
|
|
|
`PROC_DE_LOAD_16_PARAM:begin
|
2023-02-10 12:02:20 +00:00
|
|
|
if(unaligned_access==1)begin
|
2023-02-10 14:08:39 +00:00
|
|
|
PARAM1[7:0] = external_data_bus[7:0];
|
2023-02-10 12:02:20 +00:00
|
|
|
ProgCount=ProgCount+1;
|
|
|
|
state=`PROC_DE_LOAD_16_EXTRA_FETCH_SET;
|
|
|
|
end else begin
|
2023-02-10 14:08:39 +00:00
|
|
|
PARAM1[7:0] = external_data_bus[15:8];
|
|
|
|
PARAM1[15:8] = external_data_bus[7:0];
|
2023-02-10 12:02:20 +00:00
|
|
|
ProgCount=ProgCount+1;
|
|
|
|
state=`PROC_EX_STATE_ENTRY;
|
|
|
|
end
|
|
|
|
end
|
|
|
|
`PROC_DE_LOAD_16_EXTRA_FETCH:begin
|
2023-02-10 14:08:39 +00:00
|
|
|
PARAM1[15:8] = external_data_bus[15:8];
|
2023-02-09 14:46:21 +00:00
|
|
|
state=`PROC_EX_STATE_ENTRY;
|
|
|
|
end
|
2023-02-11 20:27:28 +00:00
|
|
|
`RPOC_MEMIO_READ:begin
|
|
|
|
/*Decode MOD R/M, read the data and place it to PARAM1*/
|
|
|
|
case (IN_RM)
|
|
|
|
3'b000:begin
|
|
|
|
/*[BX]+[SI]*/
|
|
|
|
`invalid_instruction
|
|
|
|
end
|
|
|
|
3'b001:begin
|
|
|
|
/*[BX]+[SI]*/
|
|
|
|
`invalid_instruction
|
|
|
|
end
|
|
|
|
3'b010:begin
|
|
|
|
/*[BP]+[SI]*/
|
|
|
|
`invalid_instruction
|
|
|
|
end
|
|
|
|
3'b011:begin
|
|
|
|
/*[BP]+[DI]*/
|
|
|
|
`invalid_instruction
|
|
|
|
end
|
|
|
|
3'b100:begin
|
|
|
|
/*[SI]*/
|
|
|
|
reg_read_addr=4'b1110;
|
|
|
|
reg_read_oe=0;
|
|
|
|
state=`PROC_MEMIO_SETADDR;
|
|
|
|
end
|
|
|
|
3'b101:begin
|
|
|
|
/*[DI]*/
|
|
|
|
reg_read_addr=4'b1111;
|
|
|
|
reg_read_oe=0;
|
|
|
|
state=`PROC_MEMIO_SETADDR;
|
|
|
|
end
|
|
|
|
3'b110:begin
|
|
|
|
/*d16 */
|
|
|
|
`invalid_instruction
|
|
|
|
end
|
|
|
|
3'b111:begin
|
|
|
|
/*[BX]*/
|
|
|
|
reg_read_addr=4'b1011;
|
|
|
|
reg_read_oe=0;
|
|
|
|
state=`PROC_MEMIO_SETADDR;
|
|
|
|
end
|
|
|
|
endcase
|
|
|
|
if(IN_MOD!=2'b00)begin
|
|
|
|
/*Actually check if 01 and add the 8bits or if 10 add the 16bits ....*/
|
|
|
|
`invalid_instruction;
|
2023-02-13 10:36:37 +00:00
|
|
|
end
|
2023-02-11 20:27:28 +00:00
|
|
|
|
2023-02-13 10:36:37 +00:00
|
|
|
end
|
|
|
|
`PROC_MEMIO_GET_ALIGNED_DATA:begin
|
|
|
|
PARAM1=(Wbit==1)? external_data_bus : {8'b00000000,external_data_bus[15:8]} ;
|
|
|
|
state=`PROC_EX_STATE_ENTRY;
|
|
|
|
end
|
|
|
|
`PROC_MEMIO_GET_UNALIGNED_DATA:begin
|
|
|
|
if(Wbit==1) begin
|
|
|
|
`invalid_instruction //easy to implement, get the other byte from the next address
|
|
|
|
end else begin
|
|
|
|
PARAM1={8'b00000000,external_data_bus[7:0]};
|
|
|
|
state=`PROC_EX_STATE_ENTRY;
|
|
|
|
end
|
|
|
|
end
|
|
|
|
`PROC_EX_STATE_ENTRY:begin
|
|
|
|
reg_write_data=ALU_1O;
|
|
|
|
FLAGS[7:0] = ALU_FLAGS[7:0];
|
|
|
|
state=`PROC_EX_STATE_EXIT;
|
|
|
|
end
|
|
|
|
endcase
|
2023-02-08 12:07:42 +00:00
|
|
|
end
|
2023-02-08 09:18:00 +00:00
|
|
|
|
2023-02-10 01:45:27 +00:00
|
|
|
|
2023-02-08 09:18:00 +00:00
|
|
|
endmodule
|